Added everything for compilation and flashing + lab 1
This commit is contained in:
AntonJ
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101
README.md
101
README.md
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@ -1,93 +1,30 @@
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# ESLabs
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## Embedded Systems Labs catalogue for MSP432
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In this repository you will find all of the labs that are required for Robot Kit using MSP432 completion during the IAS0330 course in TalTech.
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## Getting started
|
||||
|
||||
To make it easy for you to get started with GitLab, here's a list of recommended next steps.
|
||||
|
||||
Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
|
||||
|
||||
## Add your files
|
||||
|
||||
- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
|
||||
- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
|
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|
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```
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cd existing_repo
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git remote add origin https://gitlab.cs.taltech.ee/ajasts/eslabs.git
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git branch -M main
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git push -uf origin main
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```
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|
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## Integrate with your tools
|
||||
|
||||
- [ ] [Set up project integrations](https://gitlab.cs.taltech.ee/ajasts/eslabs/-/settings/integrations)
|
||||
|
||||
## Collaborate with your team
|
||||
|
||||
- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
|
||||
- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
|
||||
- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
|
||||
- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
|
||||
- [ ] [Set auto-merge](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
|
||||
|
||||
## Test and Deploy
|
||||
|
||||
Use the built-in continuous integration in GitLab.
|
||||
|
||||
- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
|
||||
- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing (SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
|
||||
- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
|
||||
- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
|
||||
- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
|
||||
|
||||
***
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# Editing this README
|
||||
|
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When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thanks to [makeareadme.com](https://www.makeareadme.com/) for this template.
|
||||
|
||||
## Suggestions for a good README
|
||||
|
||||
Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
|
||||
|
||||
## Name
|
||||
Choose a self-explaining name for your project.
|
||||
|
||||
## Description
|
||||
Let people know what your project can do specifically. Provide context and add a link to any reference visitors might be unfamiliar with. A list of Features or a Background subsection can also be added here. If there are alternatives to your project, this is a good place to list differentiating factors.
|
||||
|
||||
## Badges
|
||||
On some READMEs, you may see small images that convey metadata, such as whether or not all the tests are passing for the project. You can use Shields to add some to your README. Many services also have instructions for adding a badge.
|
||||
|
||||
## Visuals
|
||||
Depending on what you are making, it can be a good idea to include screenshots or even a video (you'll frequently see GIFs rather than actual videos). Tools like ttygif can help, but check out Asciinema for a more sophisticated method.
|
||||
|
||||
## Installation
|
||||
Within a particular ecosystem, there may be a common way of installing things, such as using Yarn, NuGet, or Homebrew. However, consider the possibility that whoever is reading your README is a novice and would like more guidance. Listing specific steps helps remove ambiguity and gets people to using your project as quickly as possible. If it only runs in a specific context like a particular programming language version or operating system or has dependencies that have to be installed manually, also add a Requirements subsection.
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## Requirements
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Linux (or WSL), VS Code, openOCD, ARM compilers (arm-none-eabi), Cortex Debug VS Code extension is required to run and debug these labs. Place the whole labs catalogue folder under msp432/simplelink_msp432p4_VERSION/. For additional information go to the [Moodle wiki](https://moodle.taltech.ee/mod/wiki/view.php?id=696448).
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## Usage
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Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README.
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Open the folder of any lab in VS Code. Open the terminal and type:
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```make```
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To build the lab code and
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```../flash.sh```
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to flash the code on to the board.
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## Support
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Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc.
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To establish UART connection, run
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```../uart.sh```
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from the lab folder (Not tested yet).
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## Roadmap
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If you have ideas for releases in the future, it is a good idea to list them in the README.
|
||||
|
||||
## Contributing
|
||||
State if you are open to contributions and what your requirements are for accepting them.
|
||||
|
||||
For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self.
|
||||
|
||||
You can also document commands to lint the code or run tests. These steps help to ensure high code quality and reduce the likelihood that the changes inadvertently break something. Having instructions for running tests is especially helpful if it requires external setup, such as starting a Selenium server for testing in a browser.
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## Lab assistance
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Anton Jaštšuk: ajasts@taltech.ee
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Uljana Reinsalu: uljana.reinsalu@taltech.ee
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## Authors and acknowledgment
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Show your appreciation to those who have contributed to the project.
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Anton Jaštšuk
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Uljana Reinsalu
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Nazrul Nazeer
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## License
|
||||
For open source projects, say how it is licensed.
|
||||
|
||||
## Project status
|
||||
If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
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Jonathan Valvano
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@ -0,0 +1,167 @@
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/******************************************************************************
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*
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* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
|
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*
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||||
* Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
|
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* GCC linker script for Texas Instruments MSP432P401R
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*
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* File creation date: 01/26/18
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*
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******************************************************************************/
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MEMORY
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{
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MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000
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INFO_FLASH (RX) : ORIGIN = 0x00200000, LENGTH = 0x00004000
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SRAM_CODE (RWX): ORIGIN = 0x01000000, LENGTH = 0x00010000
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SRAM_DATA (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000
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}
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REGION_ALIAS("REGION_TEXT", MAIN_FLASH);
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REGION_ALIAS("REGION_INFO", INFO_FLASH);
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REGION_ALIAS("REGION_BSS", SRAM_DATA);
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REGION_ALIAS("REGION_DATA", SRAM_DATA);
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REGION_ALIAS("REGION_STACK", SRAM_DATA);
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REGION_ALIAS("REGION_HEAP", SRAM_DATA);
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REGION_ALIAS("REGION_ARM_EXIDX", MAIN_FLASH);
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REGION_ALIAS("REGION_ARM_EXTAB", MAIN_FLASH);
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SECTIONS {
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/* section for the interrupt vector area */
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PROVIDE (_intvecs_base_address =
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DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x0);
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.intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {
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KEEP (*(.intvecs))
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} > REGION_TEXT
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/* The following three sections show the usage of the INFO flash memory */
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/* INFO flash memory is intended to be used for the following */
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/* device specific purposes: */
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/* Flash mailbox for device security operations */
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PROVIDE (_mailbox_base_address = 0x200000);
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.flashMailbox (_mailbox_base_address) : AT (_mailbox_base_address) {
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KEEP (*(.flashMailbox))
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} > REGION_INFO
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/* TLV table for device identification and characterization */
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PROVIDE (_tlv_base_address = 0x00201000);
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.tlvTable (_tlv_base_address) (NOLOAD) : AT (_tlv_base_address) {
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KEEP (*(.tlvTable))
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} > REGION_INFO
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/* BSL area for device bootstrap loader */
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PROVIDE (_bsl_base_address = 0x00202000);
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.bslArea (_bsl_base_address) : AT (_bsl_base_address) {
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KEEP (*(.bslArea))
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} > REGION_INFO
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PROVIDE (_vtable_base_address =
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DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000);
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.vtable (_vtable_base_address) : AT (_vtable_base_address) {
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KEEP (*(.vtable))
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} > REGION_DATA
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.text : {
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CREATE_OBJECT_SYMBOLS
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KEEP (*(.text))
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*(.text.*)
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. = ALIGN(0x4);
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KEEP (*(.ctors))
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. = ALIGN(0x4);
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KEEP (*(.dtors))
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. = ALIGN(0x4);
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__init_array_start = .;
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KEEP (*(.init_array*))
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__init_array_end = .;
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KEEP (*(.init))
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KEEP (*(.fini*))
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} > REGION_TEXT AT> REGION_TEXT
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.rodata : {
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*(.rodata)
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*(.rodata.*)
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} > REGION_TEXT AT> REGION_TEXT
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.ARM.exidx : {
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
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.ARM.extab : {
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KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*))
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} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
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__etext = .;
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.data : {
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__data_load__ = LOADADDR (.data);
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__data_start__ = .;
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KEEP (*(.data))
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KEEP (*(.data*))
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. = ALIGN (4);
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__data_end__ = .;
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} > REGION_DATA AT> REGION_TEXT
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.bss : {
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__bss_start__ = .;
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*(.shbss)
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KEEP (*(.bss))
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*(.bss.*)
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*(COMMON)
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. = ALIGN (4);
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__bss_end__ = .;
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} > REGION_BSS AT> REGION_BSS
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.heap : {
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__heap_start__ = .;
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end = __heap_start__;
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_end = end;
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__end = end;
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KEEP (*(.heap))
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__heap_end__ = .;
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__HeapLimit = __heap_end__;
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} > REGION_HEAP AT> REGION_HEAP
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.stack (NOLOAD) : ALIGN(0x8) {
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_stack = .;
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KEEP(*(.stack))
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} > REGION_STACK AT> REGION_STACK
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__StackTop = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK);
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PROVIDE(__stack = __StackTop);
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}
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@ -0,0 +1 @@
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openocd -f board/ti_msp432_launchpad.cfg -c "program lab.out verify reset exit"
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@ -0,0 +1,65 @@
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CC = arm-none-eabi-gcc
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# The location of the C compiler
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# ARMGCC_ROOT is used by some makefiles that need to know where the compiler
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# is installed.
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ARMGCC_ROOT := ${shell dirname ${shell readlink ${shell which ${CC}}}}/..
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ROOT ?= $(abspath ../..)
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OBJECTS = main.o system.o startup.o
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NAME = lab
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CFLAGS = -I.. \
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-I$(ROOT)/source \
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-I$(ROOT)/source/third_party/CMSIS/Include \
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-D__MSP432P401R__ \
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-DDeviceFamily_MSP432P401x \
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-mcpu=cortex-m4 \
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-march=armv7e-m \
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-mthumb \
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-std=c99 \
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-mfloat-abi=hard \
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-mfpu=fpv4-sp-d16 \
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-ffunction-sections \
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-fdata-sections \
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-g \
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-gstrict-dwarf \
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-Wall \
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-I$(ARMGCC_ROOT)/arm-none-eabi/include/newlib-nano \
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-I$(ARMGCC_ROOT)/arm-none-eabi/include
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LFLAGS = -Wl,-T,../config.lds \
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-Wl,-Map,$(NAME).map \
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-L$(ROOT)/source \
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-march=armv7e-m \
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-mthumb \
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-mfloat-abi=hard \
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-mfpu=fpv4-sp-d16 \
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-static \
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-Wl,--gc-sections \
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-lgcc \
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-lc \
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-lm \
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-lnosys \
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--specs=nano.specs
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all: $(NAME).out
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main.o: main.c
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@$(CC) $(CFLAGS) $< -c -o $@
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system.o: ../system.c
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@$(CC) $(CFLAGS) $< -c -o $@
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startup.o: ../startup.c
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@$(CC) $(CFLAGS) $< -c -o $@
|
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|
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$(NAME).out: $(OBJECTS)
|
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@$(CC) $(OBJECTS) $(LFLAGS) -o $(NAME).out
|
||||
|
||||
clean: # Redirecting both the stderr and stdout to /dev/null
|
||||
@rm -f $(OBJECTS) > /dev/null 2>&1
|
||||
@rm -f $(NAME).out > /dev/null 2>&1
|
||||
@rm -f $(NAME).map > /dev/null 2>&1
|
||||
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@ -0,0 +1,181 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include "ti/devices/msp432p4xx/inc/msp432p401r.h"
|
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|
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#define SW1 0x02 // on the left side of the LaunchPad board
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#define SW2 0x10 // on the right side of the LaunchPad board
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#define RED 0x01
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#define GREEN 0x02
|
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#define BLUE 0x04
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// Version 1
|
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// initialize P1.1 and P1.4 and make them inputs (P1.1 and P1.4 built-in buttons)
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// initialize P1.0 as output to red LED
|
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void Port1Init(void) {
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P1->SEL0 = 0x00;
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P1->SEL1 = 0x00; // configure P1.4 and P1.1 as GPIO
|
||||
P1->DIR = 0x01; // make P1.4 and P1.1 in, P1.0 output
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P1->REN = 0x12; // enable pull resistors on P1.4 and P1.1
|
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P1->OUT = 0x12; // P1.4 and P1.1 are pull-up
|
||||
}
|
||||
|
||||
// read P1.4, P1.1 inputs
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uint8_t Port1Input(void) {
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return P1->IN & (SW1 | SW2);
|
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}
|
||||
|
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// write output to P1.0
|
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void Port1Output(uint8_t data) {
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P1->OUT = (P1->OUT & ~0x01) | data;
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}
|
||||
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// initialize P2.2-P2.0 and make them outputs (P2.2-P2.0 built-in LEDs)
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void Port2Init(void) {
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P2->SEL0 = 0x00;
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P2->SEL1 = 0x00; // configure P2.2-P2.0 as GPIO
|
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P2->DS = 0x07; // make P2.2-P2.0 high drive strength
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||||
P2->DIR = 0x07; // make P2.2-P2.0 out
|
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P2->OUT = 0x00; // all LEDs off
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}
|
||||
|
||||
int main1(void) {
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Port1Init();
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||||
Port2Init();
|
||||
while (true) {
|
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// switches are negative logic on P1.1 and P1.4
|
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uint8_t switches = Port1Input() ^ (SW1 | SW2);
|
||||
switch (switches) {
|
||||
case SW1:
|
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P2->OUT = BLUE;
|
||||
Port1Output(1);
|
||||
break;
|
||||
case SW2:
|
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P2->OUT = RED;
|
||||
Port1Output(1);
|
||||
break;
|
||||
case SW1 | SW2:
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||||
P2->OUT = BLUE | RED;
|
||||
Port1Output(1);
|
||||
break;
|
||||
default: // neither switch pressed
|
||||
P2->OUT = 0;
|
||||
Port1Output(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Version 2
|
||||
void Port1InitFriendly(void) {
|
||||
P1->SEL0 &= ~0x13;
|
||||
P1->SEL1 &= ~0x13; // 1) configure P1.4 P1.1 P1.0 as GPIO
|
||||
P1->DIR &= ~0x12; // 2) make P1.4 and P1.1 in
|
||||
P1->DIR |= 0x01; // 2) make P1.0 out
|
||||
P1->REN |= 0x12; // 3) enable pull resistors on P1.4 and P1.1
|
||||
}
|
||||
|
||||
void Port2InitFriendly(void) {
|
||||
P2->SEL0 &= ~0x07;
|
||||
P2->SEL1 &= ~0x07; // 1) configure P2.2-P2.0 as GPIO
|
||||
P2->DIR |= 0x07; // 2) make P2.2-P2.0 out
|
||||
P2->DS |= 0x07; // 3) activate increased drive strength
|
||||
P2->OUT &= ~0x07; // all LEDs off
|
||||
}
|
||||
|
||||
// write three outputs bits of P2
|
||||
void Port2Output(uint8_t data) {
|
||||
P2->OUT = (P2->OUT & ~0x07) | data;
|
||||
}
|
||||
|
||||
int main2(void) {
|
||||
Port1InitFriendly();
|
||||
Port2InitFriendly();
|
||||
while (true) {
|
||||
// switches are negative logic on P1.1 and P1.4
|
||||
uint8_t switches = Port1Input() ^ (SW1 | SW2);
|
||||
switch (switches) {
|
||||
case SW1:
|
||||
Port2Output(BLUE);
|
||||
Port1Output(1);
|
||||
break;
|
||||
case SW2:
|
||||
Port2Output(RED);
|
||||
Port1Output(1);
|
||||
break;
|
||||
case SW1 | SW2:
|
||||
Port2Output(BLUE | RED);
|
||||
Port1Output(1);
|
||||
break;
|
||||
default: // neither switch is pressed
|
||||
Port2Output(0);
|
||||
Port1Output(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Version 3
|
||||
void SwitchInit(void) {
|
||||
P1->SEL0 &= ~0x12;
|
||||
P1->SEL1 &= ~0x12; // 1) configure P1.4 and P1.1 as GPIO
|
||||
P1->DIR &= ~0x12; // 2) make P1.4 and P1.1 in
|
||||
P1->REN |= 0x12; // 3) enable pull resistors on P1.4 and P1.1
|
||||
P1->OUT |= 0x12; // P1.4 and P1.1 are pull-up
|
||||
}
|
||||
|
||||
// bit-banded addresses, positive logic
|
||||
#define SW2IN ((*((volatile uint8_t *)(0x42098010)))^1)
|
||||
#define SW1IN ((*((volatile uint8_t *)(0x42098004)))^1)
|
||||
|
||||
void RedLEDInit(void) {
|
||||
P1->SEL0 &= ~0x01;
|
||||
P1->SEL1 &= ~0x01; // 1) configure P1.0 as GPIO
|
||||
P1->DIR |= 0x01; // 2) make P1.0 out
|
||||
}
|
||||
|
||||
// bit-banded address
|
||||
#define REDLED (*((volatile uint8_t *)(0x42098040)))
|
||||
|
||||
void ColorLEDInit(void) {
|
||||
P2->SEL0 &= ~0x07;
|
||||
P2->SEL1 &= ~0x07; // 1) configure P2.2-P2.0 as GPIO
|
||||
P2->DIR |= 0x07; // 2) make P2.2-P2.0 out
|
||||
P2->DS |= 0x07; // 3) activate increased drive strength
|
||||
P2->OUT &= ~0x07; // all LEDs off
|
||||
}
|
||||
|
||||
// bit-banded addresses
|
||||
#define BLUEOUT (*((volatile uint8_t *)(0x42098068)))
|
||||
#define GREENOUT (*((volatile uint8_t *)(0x42098064)))
|
||||
#define REDOUT (*((volatile uint8_t *)(0x42098060)))
|
||||
|
||||
int main3(void) {
|
||||
SwitchInit();
|
||||
ColorLEDInit();
|
||||
RedLEDInit();
|
||||
GREENOUT = 0;
|
||||
while (true) {
|
||||
if (SW1IN || SW2IN) {
|
||||
REDLED = 1;
|
||||
} else {
|
||||
REDLED = 0;
|
||||
}
|
||||
if (SW1IN) {
|
||||
BLUEOUT = 1;
|
||||
} else {
|
||||
BLUEOUT = 0;
|
||||
}
|
||||
if (SW2IN) {
|
||||
REDOUT = 1;
|
||||
} else {
|
||||
REDOUT = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Your solution here
|
||||
int main(void) {
|
||||
|
||||
while (true) {
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* MSP432P401R Interrupt Vector Table
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Entry point for the application. */
|
||||
extern int _mainCRTStartup();
|
||||
|
||||
/* External declaration for system initialization function */
|
||||
extern void SystemInit(void);
|
||||
|
||||
extern uint32_t __data_load__;
|
||||
extern uint32_t __data_start__;
|
||||
extern uint32_t __data_end__;
|
||||
extern uint32_t __StackTop;
|
||||
|
||||
typedef void( *pFunc )( void );
|
||||
|
||||
/* Forward declaration of the default fault handlers. */
|
||||
void Default_Handler(void);
|
||||
extern void Reset_Handler (void) __attribute__((weak));
|
||||
|
||||
/* Cortex-M4 Processor Exceptions */
|
||||
extern void NMI_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void HardFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void MemManage_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void BusFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void UsageFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void SVC_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void DebugMon_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
extern void PendSV_Handler (void) __attribute__((weak, alias("Default_Handler")));
|
||||
|
||||
/* device specific interrupt handler */
|
||||
extern void SysTick_Handler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PSS_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void CS_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PCM_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void WDT_A_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void FPU_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void FLCTL_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void COMP_E0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void COMP_E1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA0_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA0_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA1_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA1_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA2_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA2_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA3_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void TA3_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIA0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIA1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIA2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIA3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIB0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIB1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIB2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void EUSCIB3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void ADC14_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void T32_INT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void T32_INT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void T32_INTC_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void AES256_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void RTC_C_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void DMA_ERR_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void DMA_INT3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void DMA_INT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void DMA_INT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void DMA_INT0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT4_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT5_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
extern void PORT6_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
|
||||
|
||||
/* Interrupt vector table. Note that the proper constructs must be placed on this to */
|
||||
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
|
||||
/* the program if located at a start address other than 0. */
|
||||
void (* const interruptVectors[])(void) __attribute__ ((section (".intvecs"))) =
|
||||
{
|
||||
(pFunc)&__StackTop,
|
||||
/* The initial stack pointer */
|
||||
Reset_Handler, /* The reset handler */
|
||||
NMI_Handler, /* The NMI handler */
|
||||
HardFault_Handler, /* The hard fault handler */
|
||||
MemManage_Handler, /* The MPU fault handler */
|
||||
BusFault_Handler, /* The bus fault handler */
|
||||
UsageFault_Handler, /* The usage fault handler */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
0, /* Reserved */
|
||||
SVC_Handler, /* SVCall handler */
|
||||
DebugMon_Handler, /* Debug monitor handler */
|
||||
0, /* Reserved */
|
||||
PendSV_Handler, /* The PendSV handler */
|
||||
SysTick_Handler, /* The SysTick handler */
|
||||
PSS_IRQHandler, /* PSS Interrupt */
|
||||
CS_IRQHandler, /* CS Interrupt */
|
||||
PCM_IRQHandler, /* PCM Interrupt */
|
||||
WDT_A_IRQHandler, /* WDT_A Interrupt */
|
||||
FPU_IRQHandler, /* FPU Interrupt */
|
||||
FLCTL_IRQHandler, /* Flash Controller Interrupt*/
|
||||
COMP_E0_IRQHandler, /* COMP_E0 Interrupt */
|
||||
COMP_E1_IRQHandler, /* COMP_E1 Interrupt */
|
||||
TA0_0_IRQHandler, /* TA0_0 Interrupt */
|
||||
TA0_N_IRQHandler, /* TA0_N Interrupt */
|
||||
TA1_0_IRQHandler, /* TA1_0 Interrupt */
|
||||
TA1_N_IRQHandler, /* TA1_N Interrupt */
|
||||
TA2_0_IRQHandler, /* TA2_0 Interrupt */
|
||||
TA2_N_IRQHandler, /* TA2_N Interrupt */
|
||||
TA3_0_IRQHandler, /* TA3_0 Interrupt */
|
||||
TA3_N_IRQHandler, /* TA3_N Interrupt */
|
||||
EUSCIA0_IRQHandler, /* EUSCIA0 Interrupt */
|
||||
EUSCIA1_IRQHandler, /* EUSCIA1 Interrupt */
|
||||
EUSCIA2_IRQHandler, /* EUSCIA2 Interrupt */
|
||||
EUSCIA3_IRQHandler, /* EUSCIA3 Interrupt */
|
||||
EUSCIB0_IRQHandler, /* EUSCIB0 Interrupt */
|
||||
EUSCIB1_IRQHandler, /* EUSCIB1 Interrupt */
|
||||
EUSCIB2_IRQHandler, /* EUSCIB2 Interrupt */
|
||||
EUSCIB3_IRQHandler, /* EUSCIB3 Interrupt */
|
||||
ADC14_IRQHandler, /* ADC14 Interrupt */
|
||||
T32_INT1_IRQHandler, /* T32_INT1 Interrupt */
|
||||
T32_INT2_IRQHandler, /* T32_INT2 Interrupt */
|
||||
T32_INTC_IRQHandler, /* T32_INTC Interrupt */
|
||||
AES256_IRQHandler, /* AES256 Interrupt */
|
||||
RTC_C_IRQHandler, /* RTC_C Interrupt */
|
||||
DMA_ERR_IRQHandler, /* DMA_ERR Interrupt */
|
||||
DMA_INT3_IRQHandler, /* DMA_INT3 Interrupt */
|
||||
DMA_INT2_IRQHandler, /* DMA_INT2 Interrupt */
|
||||
DMA_INT1_IRQHandler, /* DMA_INT1 Interrupt */
|
||||
DMA_INT0_IRQHandler, /* DMA_INT0 Interrupt */
|
||||
PORT1_IRQHandler, /* Port1 Interrupt */
|
||||
PORT2_IRQHandler, /* Port2 Interrupt */
|
||||
PORT3_IRQHandler, /* Port3 Interrupt */
|
||||
PORT4_IRQHandler, /* Port4 Interrupt */
|
||||
PORT5_IRQHandler, /* Port5 Interrupt */
|
||||
PORT6_IRQHandler /* Port6 Interrupt */
|
||||
};
|
||||
|
||||
/* Forward declaration of the default fault handlers. */
|
||||
/* This is the code that gets called when the processor first starts execution */
|
||||
/* following a reset event. Only the absolutely necessary set is performed, */
|
||||
/* after which the application supplied entry() routine is called. Any fancy */
|
||||
/* actions (such as making decisions based on the reset cause register, and */
|
||||
/* resetting the bits in that register) are left solely in the hands of the */
|
||||
/* application. */
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pui32Src, *pui32Dest;
|
||||
|
||||
//
|
||||
// Copy the data segment initializers from flash to SRAM.
|
||||
//
|
||||
pui32Src = &__data_load__;
|
||||
for(pui32Dest = &__data_start__; pui32Dest < &__data_end__; )
|
||||
{
|
||||
*pui32Dest++ = *pui32Src++;
|
||||
}
|
||||
|
||||
/* Call system initialization routine */
|
||||
SystemInit();
|
||||
|
||||
/* Jump to the main initialization routine. */
|
||||
_mainCRTStartup();
|
||||
}
|
||||
|
||||
/* This is the code that gets called when the processor receives an unexpected */
|
||||
/* interrupt. This simply enters an infinite loop, preserving the system state */
|
||||
/* for examination by a debugger. */
|
||||
void Default_Handler(void)
|
||||
{
|
||||
/* Enter an infinite loop. */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
/******************************************************************************
|
||||
* @file system_msp432p401r.c
|
||||
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
|
||||
* MSP432P401R
|
||||
* @version 3.231
|
||||
* @date 01/26/18
|
||||
*
|
||||
* @note View configuration instructions embedded in comments
|
||||
*
|
||||
******************************************************************************/
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright (C) 2015 - 2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ti/devices/msp432p4xx/inc/msp432p401r.h"
|
||||
|
||||
/*--------------------- Configuration Instructions ----------------------------
|
||||
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
|
||||
#define __HALT_WDT 1
|
||||
2. Insert your desired CPU frequency in Hz at:
|
||||
#define __SYSTEM_CLOCK 12000000
|
||||
3. If you prefer the DC-DC power regulator (more efficient at higher
|
||||
frequencies), set the __REGULATOR to 1:
|
||||
#define __REGULATOR 1
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------- Watchdog Timer Configuration ------------------------*/
|
||||
// Halt the Watchdog Timer
|
||||
// <0> Do not halt the WDT
|
||||
// <1> Halt the WDT
|
||||
#define __HALT_WDT 1
|
||||
|
||||
/*--------------------- CPU Frequency Configuration -------------------------*/
|
||||
// CPU Frequency
|
||||
// <1500000> 1.5 MHz
|
||||
// <3000000> 3 MHz
|
||||
// <12000000> 12 MHz
|
||||
// <24000000> 24 MHz
|
||||
// <48000000> 48 MHz
|
||||
#define __SYSTEM_CLOCK 3000000
|
||||
|
||||
/*--------------------- Power Regulator Configuration -----------------------*/
|
||||
// Power Regulator Mode
|
||||
// <0> LDO
|
||||
// <1> DC-DC
|
||||
#define __REGULATOR 0
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks, used for SystemCoreClockUpdate()
|
||||
*---------------------------------------------------------------------------*/
|
||||
#define __VLOCLK 10000
|
||||
#define __MODCLK 24000000
|
||||
#define __LFXT 32768
|
||||
#define __HFXT 48000000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*---------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t source = 0, divider = 0, dividerValue = 0, centeredFreq = 0, calVal = 0;
|
||||
int16_t dcoTune = 0;
|
||||
float dcoConst = 0.0;
|
||||
|
||||
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
|
||||
dividerValue = 1 << divider;
|
||||
source = CS->CTL1 & CS_CTL1_SELM_MASK;
|
||||
|
||||
switch(source)
|
||||
{
|
||||
case CS_CTL1_SELM__LFXTCLK:
|
||||
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
|
||||
{
|
||||
// Clear interrupt flag
|
||||
CS->KEY = CS_KEY_VAL;
|
||||
CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
|
||||
CS->KEY = 1;
|
||||
|
||||
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
|
||||
{
|
||||
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
|
||||
{
|
||||
SystemCoreClock = (128000 / dividerValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = (32000 / dividerValue);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = __LFXT / dividerValue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = __LFXT / dividerValue;
|
||||
}
|
||||
break;
|
||||
case CS_CTL1_SELM__VLOCLK:
|
||||
SystemCoreClock = __VLOCLK / dividerValue;
|
||||
break;
|
||||
case CS_CTL1_SELM__REFOCLK:
|
||||
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
|
||||
{
|
||||
SystemCoreClock = (128000 / dividerValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = (32000 / dividerValue);
|
||||
}
|
||||
break;
|
||||
case CS_CTL1_SELM__DCOCLK:
|
||||
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
|
||||
|
||||
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
|
||||
{
|
||||
case CS_CTL0_DCORSEL_0:
|
||||
centeredFreq = 1500000;
|
||||
break;
|
||||
case CS_CTL0_DCORSEL_1:
|
||||
centeredFreq = 3000000;
|
||||
break;
|
||||
case CS_CTL0_DCORSEL_2:
|
||||
centeredFreq = 6000000;
|
||||
break;
|
||||
case CS_CTL0_DCORSEL_3:
|
||||
centeredFreq = 12000000;
|
||||
break;
|
||||
case CS_CTL0_DCORSEL_4:
|
||||
centeredFreq = 24000000;
|
||||
break;
|
||||
case CS_CTL0_DCORSEL_5:
|
||||
centeredFreq = 48000000;
|
||||
break;
|
||||
}
|
||||
|
||||
if(dcoTune == 0)
|
||||
{
|
||||
SystemCoreClock = centeredFreq;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
if(dcoTune & 0x1000)
|
||||
{
|
||||
dcoTune = dcoTune | 0xF000;
|
||||
}
|
||||
|
||||
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
|
||||
{
|
||||
dcoConst = *((volatile const float *) &TLV->DCOER_CONSTK_RSEL04);
|
||||
calVal = TLV->DCOER_FCAL_RSEL04;
|
||||
}
|
||||
/* Internal Resistor */
|
||||
else
|
||||
{
|
||||
dcoConst = *((volatile const float *) &TLV->DCOIR_CONSTK_RSEL04);
|
||||
calVal = TLV->DCOIR_FCAL_RSEL04;
|
||||
}
|
||||
|
||||
SystemCoreClock = (uint32_t) ((centeredFreq)
|
||||
/ (1
|
||||
- ((dcoConst * dcoTune)
|
||||
/ (8 * (1 + dcoConst * (768 - calVal))))));
|
||||
}
|
||||
break;
|
||||
case CS_CTL1_SELM__MODOSC:
|
||||
SystemCoreClock = __MODCLK / dividerValue;
|
||||
break;
|
||||
case CS_CTL1_SELM__HFXTCLK:
|
||||
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
|
||||
{
|
||||
// Clear interrupt flag
|
||||
CS->KEY = CS_KEY_VAL;
|
||||
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
|
||||
CS->KEY = 1;
|
||||
|
||||
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
|
||||
{
|
||||
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
|
||||
{
|
||||
SystemCoreClock = (128000 / dividerValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = (32000 / dividerValue);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = __HFXT / dividerValue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = __HFXT / dividerValue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Performs the following initialization steps:
|
||||
* 1. Enables the FPU
|
||||
* 2. Halts the WDT if requested
|
||||
* 3. Enables all SRAM banks
|
||||
* 4. Sets up power regulator and VCORE
|
||||
* 5. Enable Flash wait states if needed
|
||||
* 6. Change MCLK to desired frequency
|
||||
* 7. Enable Flash read buffering
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Enable FPU if used
|
||||
#if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access
|
||||
(3UL << 11 * 2)); // Set CP11 Full Access
|
||||
#endif
|
||||
|
||||
#if (__HALT_WDT == 1)
|
||||
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
|
||||
#endif
|
||||
|
||||
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
|
||||
|
||||
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
|
||||
// Default VCORE is LDO VCORE0 so no change necessary
|
||||
|
||||
// Switches LDO VCORE0 to DCDC VCORE0 if requested
|
||||
#if __REGULATOR
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
#endif
|
||||
|
||||
// No flash wait states necessary
|
||||
|
||||
// DCO = 1.5 MHz; MCLK = source
|
||||
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
|
||||
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
|
||||
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
|
||||
// Select MCLK as DCO source
|
||||
CS->KEY = 0;
|
||||
|
||||
// Set Flash Bank read buffering
|
||||
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
|
||||
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
|
||||
|
||||
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
|
||||
// Default VCORE is LDO VCORE0 so no change necessary
|
||||
|
||||
// Switches LDO VCORE0 to DCDC VCORE0 if requested
|
||||
#if __REGULATOR
|
||||
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
|
||||
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
|
||||
#endif
|
||||
|
||||
// No flash wait states necessary
|
||||
|
||||
// DCO = 3 MHz; MCLK = source
|
||||
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
|
||||
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
|
||||
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
|
||||
// Select MCLK as DCO source
|
||||
CS->KEY = 0;
|
||||
|
||||
// Set Flash Bank read buffering
|
||||
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
|
||||
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
|
||||
|
||||
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
|
||||
// Default VCORE is LDO VCORE0 so no change necessary
|
||||
|
||||
// Switches LDO VCORE0 to DCDC VCORE0 if requested
|
||||
#if __REGULATOR
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
#endif
|
||||
|
||||
// No flash wait states necessary
|
||||
|
||||
// DCO = 12 MHz; MCLK = source
|
||||
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
|
||||
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
|
||||
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
|
||||
// Select MCLK as DCO source
|
||||
CS->KEY = 0;
|
||||
|
||||
// Set Flash Bank read buffering
|
||||
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
|
||||
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
|
||||
|
||||
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
|
||||
// Default VCORE is LDO VCORE0 so no change necessary
|
||||
|
||||
// Switches LDO VCORE0 to DCDC VCORE0 if requested
|
||||
#if __REGULATOR
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
#endif
|
||||
|
||||
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
|
||||
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
|
||||
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
|
||||
|
||||
// DCO = 24 MHz; MCLK = source
|
||||
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
|
||||
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
|
||||
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
|
||||
// Select MCLK as DCO source
|
||||
CS->KEY = 0;
|
||||
|
||||
// Set Flash Bank read buffering
|
||||
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
|
||||
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
|
||||
|
||||
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
|
||||
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
|
||||
// Switches LDO VCORE1 to DCDC VCORE1 if requested
|
||||
#if __REGULATOR
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
|
||||
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
|
||||
#endif
|
||||
|
||||
// 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
|
||||
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
|
||||
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
|
||||
|
||||
// DCO = 48 MHz; MCLK = source
|
||||
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
|
||||
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
|
||||
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
|
||||
// Select MCLK as DCO source
|
||||
CS->KEY = 0;
|
||||
|
||||
// Set Flash Bank read buffering
|
||||
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
|
||||
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
sudo service udev restart
|
||||
sudo udevadm control --reload
|
||||
sudo udevadm trigger
|
||||
Loading…
Reference in New Issue