From d15910c62e81e5a19117e3cd4b5d7fac1d43e037 Mon Sep 17 00:00:00 2001 From: AntonJ Date: Mon, 17 Feb 2025 10:43:24 +0200 Subject: [PATCH] Separate from SDK git repo, Lab 1 working --- inc/cmsis_compiler.h | 271 ++ inc/cmsis_gcc.h | 2101 +++++++++++ inc/cmsis_version.h | 39 + inc/core_cm4.h | 2121 +++++++++++ inc/mpu_armv7.h | 272 ++ inc/msp432p401r.h | 6967 +++++++++++++++++++++++++++++++++++++ inc/msp432p401r_classic.h | 3623 +++++++++++++++++++ inc/msp_compatibility.h | 326 ++ inc/system_msp432p401r.h | 92 + lab1/Makefile | 4 +- lab1/main.c | 2 +- system.c | 2 +- 12 files changed, 15816 insertions(+), 4 deletions(-) create mode 100644 inc/cmsis_compiler.h create mode 100644 inc/cmsis_gcc.h create mode 100644 inc/cmsis_version.h create mode 100644 inc/core_cm4.h create mode 100644 inc/mpu_armv7.h create mode 100644 inc/msp432p401r.h create mode 100644 inc/msp432p401r_classic.h create mode 100644 inc/msp_compatibility.h create mode 100644 inc/system_msp432p401r.h diff --git a/inc/cmsis_compiler.h b/inc/cmsis_compiler.h new file mode 100644 index 0000000..fdb1a97 --- /dev/null +++ b/inc/cmsis_compiler.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/inc/cmsis_gcc.h b/inc/cmsis_gcc.h new file mode 100644 index 0000000..d86b0a2 --- /dev/null +++ b/inc/cmsis_gcc.h @@ -0,0 +1,2101 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.1.0 + * @date 20. December 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/inc/cmsis_version.h b/inc/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/inc/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/inc/core_cm4.h b/inc/core_cm4.h new file mode 100644 index 0000000..f205b33 --- /dev/null +++ b/inc/core_cm4.h @@ -0,0 +1,2121 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/inc/mpu_armv7.h b/inc/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/inc/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/inc/msp432p401r.h b/inc/msp432p401r.h new file mode 100644 index 0000000..31cb484 --- /dev/null +++ b/inc/msp432p401r.h @@ -0,0 +1,6967 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* MSP432P401R Register Definitions +* +* This file includes CMSIS compliant component and register definitions +* +* For legacy components the definitions that are compatible with MSP430 code, +* are included with msp432p401r_classic.h +* +* With CMSIS definitions, the register defines have been reformatted: +* ModuleName[ModuleInstance]->RegisterName +* +* Writing to CMSIS bit fields can be done through register level +* or via bitband area access: +* - ADC14->CTL0 |= ADC14_CTL0_ENC; +* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; +* +* File creation date: 2018-01-26 +* +******************************************************************************/ + +#ifndef __MSP432P401R_H__ +#define __MSP432P401R_H__ + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define __MSP432_HEADER_VERSION__ 3231 + +/* Remap MSP432 intrinsics to ARM equivalents */ +#include "msp_compatibility.h" + +/****************************************************************************** +* include MSP430 legacy definitions to make porting of code from MSP430 * +* code base easier * +* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * +* your project to omit including the classic defines * +******************************************************************************/ +#ifndef NO_MSP_CLASSIC_DEFINES +#include "msp432p401r_classic.h" +#endif + + +#ifndef __CMSIS_CONFIG__ +#define __CMSIS_CONFIG__ + +/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions + This file defines all structures and symbols for MSP432P401R: + - components and registers + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + +/****************************************************************************** +* Processor and Core Peripherals * +******************************************************************************/ +/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/****************************************************************************** +* CMSIS-compatible Interrupt Number Definition * +******************************************************************************/ +typedef enum IRQn +{ + /* Cortex-M4 Processor Exceptions Numbers */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + /* Peripheral Exceptions Numbers */ + PSS_IRQn = 0, /* 16 PSS Interrupt */ + CS_IRQn = 1, /* 17 CS Interrupt */ + PCM_IRQn = 2, /* 18 PCM Interrupt */ + WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ + FPU_IRQn = 4, /* 20 FPU Interrupt */ + FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ + COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ + COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ + TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ + TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ + TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ + TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ + TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ + TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ + TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ + TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ + EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ + EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ + EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ + EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ + EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ + EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ + EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ + EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ + ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ + T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ + T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ + T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ + AES256_IRQn = 28, /* 44 AES256 Interrupt */ + RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ + DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ + DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ + DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ + DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ + DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ + PORT1_IRQn = 35, /* 51 Port1 Interrupt */ + PORT2_IRQn = 36, /* 52 Port2 Interrupt */ + PORT3_IRQn = 37, /* 53 Port3 Interrupt */ + PORT4_IRQn = 38, /* 54 Port4 Interrupt */ + PORT5_IRQn = 39, /* 55 Port5 Interrupt */ + PORT6_IRQn = 40 /* 56 Port6 Interrupt */ +} IRQn_Type; + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ +#define __CM4_REV 0x0001 /* Core revision r0p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present or not */ + +/****************************************************************************** +* Available Peripherals * +******************************************************************************/ +#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ +#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ +#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ +#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ +#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ +#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ +#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ +#define __MCU_HAS_CS__ /*!< Module CS is available */ +#define __MCU_HAS_DIO__ /*!< Module DIO is available */ +#define __MCU_HAS_DMA__ /*!< Module DMA is available */ +#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ +#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ +#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ +#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ +#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ +#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ +#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ +#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ +#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ +#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ +#define __MCU_HAS_PCM__ /*!< Module PCM is available */ +#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ +#define __MCU_HAS_PSS__ /*!< Module PSS is available */ +#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ +#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ +#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ +#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ +#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ +#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ +#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ +#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ +#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ +#define __MCU_HAS_TLV__ /*!< Module TLV is available */ +#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ + +/* Definitions to show that specific ports are available */ + +#define __MSP432_HAS_PORTA_R__ +#define __MSP432_HAS_PORTB_R__ +#define __MSP432_HAS_PORTC_R__ +#define __MSP432_HAS_PORTD_R__ +#define __MSP432_HAS_PORTE_R__ +#define __MSP432_HAS_PORTJ_R__ + +#define __MSP432_HAS_PORT1_R__ +#define __MSP432_HAS_PORT2_R__ +#define __MSP432_HAS_PORT3_R__ +#define __MSP432_HAS_PORT4_R__ +#define __MSP432_HAS_PORT5_R__ +#define __MSP432_HAS_PORT6_R__ +#define __MSP432_HAS_PORT7_R__ +#define __MSP432_HAS_PORT8_R__ +#define __MSP432_HAS_PORT9_R__ +#define __MSP432_HAS_PORT10_R__ + + +/*@}*/ /* end of group MSP432P401R_CMSIS */ + +/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ +#ifdef __TI_ARM__ +/* disable the TI ULP advisor check for the core header file definitions */ +#pragma diag_push +#pragma CHECK_ULP("none") +#include "core_cm4.h" +#pragma diag_pop +#else +#include "core_cm4.h" +#endif + +/* System Header */ +#include "system_msp432p401r.h" + +/****************************************************************************** +* Definition of standard bits * +******************************************************************************/ +#define BIT0 (uint16_t)(0x0001) +#define BIT1 (uint16_t)(0x0002) +#define BIT2 (uint16_t)(0x0004) +#define BIT3 (uint16_t)(0x0008) +#define BIT4 (uint16_t)(0x0010) +#define BIT5 (uint16_t)(0x0020) +#define BIT6 (uint16_t)(0x0040) +#define BIT7 (uint16_t)(0x0080) +#define BIT8 (uint16_t)(0x0100) +#define BIT9 (uint16_t)(0x0200) +#define BITA (uint16_t)(0x0400) +#define BITB (uint16_t)(0x0800) +#define BITC (uint16_t)(0x1000) +#define BITD (uint16_t)(0x2000) +#define BITE (uint16_t)(0x4000) +#define BITF (uint16_t)(0x8000) +#define BIT(x) ((uint16_t)1 << (x)) + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping + @{ +*/ + +#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ +#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ + +#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ +#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ +#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ +#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ +#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ +#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ +#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ +#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ +#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ +#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ +#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ +#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ +#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ +#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ +#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ +#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ +#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ +#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ +#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ +#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ +#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ +#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ +#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ +#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ +#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ +#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ +#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ +#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ +#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ +#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ +#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ +#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ +#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ +#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ +#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ +#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ +#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ +#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ +#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ +#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ +#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ +#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ +#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ + + +/*@}*/ /* end of group MSP432P401R_MemoryMap */ + +/****************************************************************************** +* Definitions for bit band access * +******************************************************************************/ +#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) +#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) + +/* SRAM allows 32 bit bit band access */ +#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) +/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ +#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) + +/****************************************************************************** +* Peripheral register definitions * +******************************************************************************/ +/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals + MSP432P401R Device Specific Peripheral registers structures + @{ +*/ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TI_ARM__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* ADC14 Registers +******************************************************************************/ +/** @addtogroup ADC14 MSP432P401R (ADC14) + @{ +*/ +typedef struct { + __IO uint32_t CTL0; /*!< Control 0 Register */ + __IO uint32_t CTL1; /*!< Control 1 Register */ + __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ + __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ + __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ + __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ + __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ + __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ + uint32_t RESERVED0[9]; + __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ + __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ + __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ + __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ + __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ + __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ + __IO uint32_t IV; /*!< Interrupt Vector Register */ +} ADC14_Type; + +/*@}*/ /* end of group ADC14 */ + + +/****************************************************************************** +* AES256 Registers +******************************************************************************/ +/** @addtogroup AES256 MSP432P401R (AES256) + @{ +*/ +typedef struct { + __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ + __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ + __IO uint16_t STAT; /*!< AES Accelerator Status Register */ + __O uint16_t KEY; /*!< AES Accelerator Key Register */ + __O uint16_t DIN; /*!< AES Accelerator Data In Register */ + __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ + __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ + __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ +} AES256_Type; + +/*@}*/ /* end of group AES256 */ + + +/****************************************************************************** +* CAPTIO Registers +******************************************************************************/ +/** @addtogroup CAPTIO MSP432P401R (CAPTIO) + @{ +*/ +typedef struct { + uint16_t RESERVED0[7]; + __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ +} CAPTIO_Type; + +/*@}*/ /* end of group CAPTIO */ + + +/****************************************************************************** +* COMP_E Registers +******************************************************************************/ +/** @addtogroup COMP_E MSP432P401R (COMP_E) + @{ +*/ +typedef struct { + __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ + __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ + __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ + __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ + uint16_t RESERVED0[2]; + __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ + __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ +} COMP_E_Type; + +/*@}*/ /* end of group COMP_E */ + + +/****************************************************************************** +* CRC32 Registers +******************************************************************************/ +/** @addtogroup CRC32 MSP432P401R (CRC32) + @{ +*/ +typedef struct { + __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ + uint16_t RESERVED0; + __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ + uint16_t RESERVED1; + __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ + __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ + __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ + __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ + __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ + uint16_t RESERVED2; + __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ + uint16_t RESERVED3; + __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ + uint16_t RESERVED4[2]; + __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ +} CRC32_Type; + +/*@}*/ /* end of group CRC32 */ + + +/****************************************************************************** +* CS Registers +******************************************************************************/ +/** @addtogroup CS MSP432P401R (CS) + @{ +*/ +typedef struct { + __IO uint32_t KEY; /*!< Key Register */ + __IO uint32_t CTL0; /*!< Control 0 Register */ + __IO uint32_t CTL1; /*!< Control 1 Register */ + __IO uint32_t CTL2; /*!< Control 2 Register */ + __IO uint32_t CTL3; /*!< Control 3 Register */ + uint32_t RESERVED0[7]; + __IO uint32_t CLKEN; /*!< Clock Enable Register */ + __I uint32_t STAT; /*!< Status Register */ + uint32_t RESERVED1[2]; + __IO uint32_t IE; /*!< Interrupt Enable Register */ + uint32_t RESERVED2; + __I uint32_t IFG; /*!< Interrupt Flag Register */ + uint32_t RESERVED3; + __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ + uint32_t RESERVED4; + __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ + uint32_t RESERVED5; + __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ + __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ +} CS_Type; + +/*@}*/ /* end of group CS */ + + +/****************************************************************************** +* DIO Registers +******************************************************************************/ +/** @addtogroup DIO MSP432P401R (DIO) + @{ +*/ +typedef struct { + union { + __I uint16_t IN; /*!< Port Pair Input */ + struct { + __I uint8_t IN_L; /*!< Low Port Input */ + __I uint8_t IN_H; /*!< High Port Input */ + }; + }; + union { + __IO uint16_t OUT; /*!< Port Pair Output */ + struct { + __IO uint8_t OUT_L; /*!< Low Port Output */ + __IO uint8_t OUT_H; /*!< High Port Output */ + }; + }; + union { + __IO uint16_t DIR; /*!< Port Pair Direction */ + struct { + __IO uint8_t DIR_L; /*!< Low Port Direction */ + __IO uint8_t DIR_H; /*!< High Port Direction */ + }; + }; + union { + __IO uint16_t REN; /*!< Port Pair Resistor Enable */ + struct { + __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ + __IO uint8_t REN_H; /*!< High Port Resistor Enable */ + }; + }; + union { + __IO uint16_t DS; /*!< Port Pair Drive Strength */ + struct { + __IO uint8_t DS_L; /*!< Low Port Drive Strength */ + __IO uint8_t DS_H; /*!< High Port Drive Strength */ + }; + }; + union { + __IO uint16_t SEL0; /*!< Port Pair Select 0 */ + struct { + __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ + __IO uint8_t SEL0_H; /*!< High Port Select 0 */ + }; + }; + union { + __IO uint16_t SEL1; /*!< Port Pair Select 1 */ + struct { + __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ + __IO uint8_t SEL1_H; /*!< High Port Select 1 */ + }; + }; + __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ + uint16_t RESERVED0[3]; + union { + __IO uint16_t SELC; /*!< Port Pair Complement Select */ + struct { + __IO uint8_t SELC_L; /*!< Low Port Complement Select */ + __IO uint8_t SELC_H; /*!< High Port Complement Select */ + }; + }; + union { + __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ + struct { + __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ + __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ + }; + }; + union { + __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ + struct { + __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ + __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ + }; + }; + union { + __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ + struct { + __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ + __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ + }; + }; + __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ +} DIO_PORT_Interruptable_Type; + +typedef struct { + union { + __I uint16_t IN; /*!< Port Pair Input */ + struct { + __I uint8_t IN_L; /*!< Low Port Input */ + __I uint8_t IN_H; /*!< High Port Input */ + }; + }; + union { + __IO uint16_t OUT; /*!< Port Pair Output */ + struct { + __IO uint8_t OUT_L; /*!< Low Port Output */ + __IO uint8_t OUT_H; /*!< High Port Output */ + }; + }; + union { + __IO uint16_t DIR; /*!< Port Pair Direction */ + struct { + __IO uint8_t DIR_L; /*!< Low Port Direction */ + __IO uint8_t DIR_H; /*!< High Port Direction */ + }; + }; + union { + __IO uint16_t REN; /*!< Port Pair Resistor Enable */ + struct { + __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ + __IO uint8_t REN_H; /*!< High Port Resistor Enable */ + }; + }; + union { + __IO uint16_t DS; /*!< Port Pair Drive Strength */ + struct { + __IO uint8_t DS_L; /*!< Low Port Drive Strength */ + __IO uint8_t DS_H; /*!< High Port Drive Strength */ + }; + }; + union { + __IO uint16_t SEL0; /*!< Port Pair Select 0 */ + struct { + __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ + __IO uint8_t SEL0_H; /*!< High Port Select 0 */ + }; + }; + union { + __IO uint16_t SEL1; /*!< Port Pair Select 1 */ + struct { + __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ + __IO uint8_t SEL1_H; /*!< High Port Select 1 */ + }; + }; + uint16_t RESERVED0[4]; + union { + __IO uint16_t SELC; /*!< Port Pair Complement Select */ + struct { + __IO uint8_t SELC_L; /*!< Low Port Complement Select */ + __IO uint8_t SELC_H; /*!< High Port Complement Select */ + }; + }; +} DIO_PORT_Not_Interruptable_Type; + + +typedef struct { + __I uint8_t IN; /*!< Port Input */ + uint8_t RESERVED0; + __IO uint8_t OUT; /*!< Port Output */ + uint8_t RESERVED1; + __IO uint8_t DIR; /*!< Port Direction */ + uint8_t RESERVED2; + __IO uint8_t REN; /*!< Port Resistor Enable */ + uint8_t RESERVED3; + __IO uint8_t DS; /*!< Port Drive Strength */ + uint8_t RESERVED4; + __IO uint8_t SEL0; /*!< Port Select 0 */ + uint8_t RESERVED5; + __IO uint8_t SEL1; /*!< Port Select 1 */ + uint8_t RESERVED6; + __I uint16_t IV; /*!< Port Interrupt Vector Value */ + uint8_t RESERVED7[6]; + __IO uint8_t SELC; /*!< Port Complement Select */ + uint8_t RESERVED8; + __IO uint8_t IES; /*!< Port Interrupt Edge Select */ + uint8_t RESERVED9; + __IO uint8_t IE; /*!< Port Interrupt Enable */ + uint8_t RESERVED10; + __IO uint8_t IFG; /*!< Port Interrupt Flag */ + uint8_t RESERVED11; +} DIO_PORT_Odd_Interruptable_Type; + +typedef struct { + uint8_t RESERVED0; + __I uint8_t IN; /*!< Port Input */ + uint8_t RESERVED1; + __IO uint8_t OUT; /*!< Port Output */ + uint8_t RESERVED2; + __IO uint8_t DIR; /*!< Port Direction */ + uint8_t RESERVED3; + __IO uint8_t REN; /*!< Port Resistor Enable */ + uint8_t RESERVED4; + __IO uint8_t DS; /*!< Port Drive Strength */ + uint8_t RESERVED5; + __IO uint8_t SEL0; /*!< Port Select 0 */ + uint8_t RESERVED6; + __IO uint8_t SEL1; /*!< Port Select 1 */ + uint8_t RESERVED7[9]; + __IO uint8_t SELC; /*!< Port Complement Select */ + uint8_t RESERVED8; + __IO uint8_t IES; /*!< Port Interrupt Edge Select */ + uint8_t RESERVED9; + __IO uint8_t IE; /*!< Port Interrupt Enable */ + uint8_t RESERVED10; + __IO uint8_t IFG; /*!< Port Interrupt Flag */ + __I uint16_t IV; /*!< Port Interrupt Vector Value */ +} DIO_PORT_Even_Interruptable_Type; + +/*@}*/ /* end of group MSP432P401R_DIO */ + + +/****************************************************************************** +* DMA Registers +******************************************************************************/ +/** @addtogroup DMA MSP432P401R (DMA) + @{ +*/ +typedef struct { + __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ + __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ + uint32_t RESERVED0[2]; + __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ + uint32_t RESERVED1[28]; + __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ + __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ + __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ + uint32_t RESERVED2; + __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ + __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ +} DMA_Channel_Type; + +typedef struct { + __I uint32_t STAT; /*!< Status Register */ + __O uint32_t CFG; /*!< Configuration Register */ + __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ + __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ + __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ + __O uint32_t SWREQ; /*!< Channel Software Request Register */ + __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ + __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ + __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ + __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ + __IO uint32_t ENASET; /*!< Channel Enable Set Register */ + __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ + __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ + __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ + __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ + __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ + uint32_t RESERVED4[3]; + __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ +} DMA_Control_Type; + +/*@}*/ /* end of group DMA */ + + +/****************************************************************************** +* EUSCI_A Registers +******************************************************************************/ +/** @addtogroup EUSCI_A MSP432P401R (EUSCI_A) + @{ +*/ +typedef struct { + __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ + __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ + uint16_t RESERVED0; + __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ + __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ + __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ + __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ + __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ + __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ + __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ + uint16_t RESERVED1[3]; + __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ + __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ + __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ +} EUSCI_A_Type; + +/*@}*/ /* end of group EUSCI_A */ + +/** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI) + @{ +*/ +typedef struct { + __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ + uint16_t RESERVED0[2]; + __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ + uint16_t RESERVED1; + __IO uint16_t STATW; + __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ + __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ + uint16_t RESERVED2[5]; + __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ + __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ + __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ +} EUSCI_A_SPI_Type; + +/*@}*/ /* end of group EUSCI_A_SPI */ + + +/****************************************************************************** +* EUSCI_B Registers +******************************************************************************/ +/** @addtogroup EUSCI_B MSP432P401R (EUSCI_B) + @{ +*/ +typedef struct { + __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ + __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ + uint16_t RESERVED0; + __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ + __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ + __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ + __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ + __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ + uint16_t RESERVED1[2]; + __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ + __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ + __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ + __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ + __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ + __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ + __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ + uint16_t RESERVED2[4]; + __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ + __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ + __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ +} EUSCI_B_Type; + +/*@}*/ /* end of group EUSCI_B */ + +/** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI) + @{ +*/ +typedef struct { + __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ + uint16_t RESERVED0[2]; + __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ + __IO uint16_t STATW; + uint16_t RESERVED1; + __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ + __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ + uint16_t RESERVED2[13]; + __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ + __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ + __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ +} EUSCI_B_SPI_Type; + +/*@}*/ /* end of group EUSCI_B_SPI */ + + +/****************************************************************************** +* FLCTL Registers +******************************************************************************/ +/** @addtogroup FLCTL MSP432P401R (FLCTL) + @{ +*/ +typedef struct { + __I uint32_t POWER_STAT; /*!< Power Status Register */ + uint32_t RESERVED0[3]; + __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ + __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ + uint32_t RESERVED1[2]; + __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ + __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ + __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ + uint32_t RESERVED2[4]; + __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ + __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ + uint32_t RESERVED3[3]; + __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ + __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ + __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ + uint32_t RESERVED4; + __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ + __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ + __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ + __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ + __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ + __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ + __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ + __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ + __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ + __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ + __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ + __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ + __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ + __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ + __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ + __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ + __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ + __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ + uint32_t RESERVED5[2]; + __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ + __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ + uint32_t RESERVED6[2]; + __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ + __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ + uint32_t RESERVED7[2]; + __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ + __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ + __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ + __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ + uint32_t RESERVED8[4]; + __IO uint32_t IFG; /*!< Interrupt Flag Register */ + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ + __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ + __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ + __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ + __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ + __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ + __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ + __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ + __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ + __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ + __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ +} FLCTL_Type; + +/*@}*/ /* end of group FLCTL */ + + +/****************************************************************************** +* FL_BOOTOVER_MAILBOX Registers +******************************************************************************/ +/** @addtogroup SEC_ZONE_PARAMS MSP432P401R (FL_BOOTOVER_MAILBOX) + @{ +*/ +typedef struct { + __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ + __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ + __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ + __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ + __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ + __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ + __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ + __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ + __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ + uint32_t RESERVED0[2]; +} SEC_ZONE_PARAMS_Type; + +/*@}*/ /* end of group SEC_ZONE_PARAMS */ + +/** @addtogroup SEC_ZONE_UPDATE MSP432P401R (FL_BOOTOVER_MAILBOX) + @{ +*/ +typedef struct { + __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ + __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ + __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ + uint32_t RESERVED0; +} SEC_ZONE_UPDATE_Type; + +/*@}*/ /* end of group SEC_ZONE_UPDATE */ + +/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401R (FL_BOOTOVER_MAILBOX) + @{ +*/ +typedef struct { + __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ + __IO uint32_t CMD; /*!< Command for Boot override operations. */ + uint32_t RESERVED0[2]; + __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ + __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ + __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ + __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ + __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ + uint32_t RESERVED1[2]; + SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; + __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ + __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ + __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ + uint32_t RESERVED2[2]; + __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ + __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ + __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ + __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ + __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ + uint32_t RESERVED3; + SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; + uint32_t RESERVED4; + __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ + __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ + __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ + __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ + uint32_t RESERVED5; + __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ + __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ + uint32_t RESERVED6[2]; + __IO uint32_t MB_END; /*!< Mailbox end */ +} FL_BOOTOVER_MAILBOX_Type; + +/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ + + +/****************************************************************************** +* PCM Registers +******************************************************************************/ +/** @addtogroup PCM MSP432P401R (PCM) + @{ +*/ +typedef struct { + __IO uint32_t CTL0; /*!< Control 0 Register */ + __IO uint32_t CTL1; /*!< Control 1 Register */ + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __I uint32_t IFG; /*!< Interrupt Flag Register */ + __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ +} PCM_Type; + +/*@}*/ /* end of group PCM */ + + +/****************************************************************************** +* PMAP Registers +******************************************************************************/ +/** @addtogroup PMAP MSP432P401R (PMAP) + @{ +*/ +typedef struct { + __IO uint16_t KEYID; + __IO uint16_t CTL; +} PMAP_COMMON_Type; + +typedef struct { + union { + __IO uint16_t PMAP_REGISTER[4]; + struct { + __IO uint8_t PMAP_REGISTER0; + __IO uint8_t PMAP_REGISTER1; + __IO uint8_t PMAP_REGISTER2; + __IO uint8_t PMAP_REGISTER3; + __IO uint8_t PMAP_REGISTER4; + __IO uint8_t PMAP_REGISTER5; + __IO uint8_t PMAP_REGISTER6; + __IO uint8_t PMAP_REGISTER7; + }; + }; +} PMAP_REGISTER_Type; + +/*@}*/ /* end of group PMAP */ + + +/****************************************************************************** +* PSS Registers +******************************************************************************/ +/** @addtogroup PSS MSP432P401R (PSS) + @{ +*/ +typedef struct { + __IO uint32_t KEY; /*!< Key Register */ + __IO uint32_t CTL0; /*!< Control 0 Register */ + uint32_t RESERVED0[11]; + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __I uint32_t IFG; /*!< Interrupt Flag Register */ + __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ +} PSS_Type; + +/*@}*/ /* end of group PSS */ + + +/****************************************************************************** +* REF_A Registers +******************************************************************************/ +/** @addtogroup REF_A MSP432P401R (REF_A) + @{ +*/ +typedef struct { + __IO uint16_t CTL0; /*!< REF Control Register 0 */ +} REF_A_Type; + +/*@}*/ /* end of group REF_A */ + + +/****************************************************************************** +* RSTCTL Registers +******************************************************************************/ +/** @addtogroup RSTCTL MSP432P401R (RSTCTL) + @{ +*/ +typedef struct { + __IO uint32_t RESET_REQ; /*!< Reset Request Register */ + __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ + __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ + __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ + __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ + __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ + __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ + uint32_t RESERVED0[57]; + __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ + __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ + __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ + __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ + __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ + __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ + __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ + __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ + __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ + __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ +} RSTCTL_Type; + +/*@}*/ /* end of group RSTCTL */ + + +/****************************************************************************** +* RTC_C Registers +******************************************************************************/ +/** @addtogroup RTC_C MSP432P401R (RTC_C) + @{ +*/ +typedef struct { + __IO uint16_t CTL0; /*!< RTCCTL0 Register */ + __IO uint16_t CTL13; /*!< RTCCTL13 Register */ + __IO uint16_t OCAL; /*!< RTCOCAL Register */ + __IO uint16_t TCMP; /*!< RTCTCMP Register */ + __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ + __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ + __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ + __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ + __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ + __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ + __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ + __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ + __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ + __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ + __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ + __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ +} RTC_C_Type; + +/*@}*/ /* end of group RTC_C */ + +/** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD) + @{ +*/ +typedef struct { + uint16_t RESERVED0[8]; + __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ + __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ + __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ + __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ + __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ + __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ +} RTC_C_BCD_Type; + +/*@}*/ /* end of group RTC_C_BCD */ + + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +/** @addtogroup SYSCTL MSP432P401R (SYSCTL) + @{ +*/ +typedef struct { + __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ + __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ + __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ + __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ + __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ + __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ + __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ + uint32_t RESERVED0; + __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ + uint32_t RESERVED1[3]; + __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ + uint32_t RESERVED2[3]; + __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ +} SYSCTL_Type; + +typedef struct { + __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ + __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ + __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ + __IO uint32_t RESET_REQ; /*!< Reset Request Register */ + __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ + uint32_t RESERVED7[2]; + __I uint32_t SYSTEM_STAT; /*!< System Status Register */ +} SYSCTL_Boot_Type; + +/*@}*/ /* end of group SYSCTL */ + + +/****************************************************************************** +* Timer32 Registers +******************************************************************************/ +/** @addtogroup Timer32 MSP432P401R (Timer32) + @{ +*/ +typedef struct { + __IO uint32_t LOAD; /*!< Timer Load Register */ + __I uint32_t VALUE; /*!< Timer Current Value Register */ + __IO uint32_t CONTROL; /*!< Timer Control Register */ + __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ + __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< Timer Interrupt Status Register */ + __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ +} Timer32_Type; + +/*@}*/ /* end of group Timer32 */ + + +/****************************************************************************** +* Timer_A Registers +******************************************************************************/ +/** @addtogroup Timer_A MSP432P401R (Timer_A) + @{ +*/ +typedef struct { + __IO uint16_t CTL; /*!< TimerAx Control Register */ + __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ + uint16_t RESERVED0[2]; + __IO uint16_t R; /*!< TimerA register */ + __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ + uint16_t RESERVED1[2]; + __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ + uint16_t RESERVED2[6]; + __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ +} Timer_A_Type; + +/*@}*/ /* end of group Timer_A */ + + +/****************************************************************************** +* TLV Registers +******************************************************************************/ +/** @addtogroup TLV MSP432P401R (TLV) + @{ +*/ +typedef struct { + __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ + __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ + __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ + __I uint32_t DEVICE_ID; /*!< Device ID */ + __I uint32_t HWREV; /*!< HW Revision */ + __I uint32_t BCREV; /*!< Boot Code Revision */ + __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ + __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ + __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ + __I uint32_t DIE_XPOS; /*!< Die X-Position */ + __I uint32_t DIE_YPOS; /*!< Die Y-Position */ + __I uint32_t WAFER_ID; /*!< Wafer ID */ + __I uint32_t LOT_ID; /*!< Lot ID */ + __I uint32_t RESERVED0; /*!< Reserved */ + __I uint32_t RESERVED1; /*!< Reserved */ + __I uint32_t RESERVED2; /*!< Reserved */ + __I uint32_t TEST_RESULTS; /*!< Test Results */ + __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ + __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ + __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ + __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ + __I uint32_t RESERVED3; /*!< Reserved */ + __I uint32_t RESERVED4; /*!< Reserved */ + __I uint32_t RESERVED5; /*!< Reserved */ + __I uint32_t RESERVED6; /*!< Reserved */ + __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ + __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ + __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ + __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ + __I uint32_t RESERVED7; /*!< Reserved */ + __I uint32_t RESERVED8; /*!< Reserved */ + __I uint32_t RESERVED9; /*!< Reserved */ + __I uint32_t RESERVED10; /*!< Reserved */ + __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ + __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ + __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ + __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ + __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ + __I uint32_t ADC_OFFSET; /*!< ADC Offset */ + __I uint32_t RESERVED11; /*!< Reserved */ + __I uint32_t RESERVED12; /*!< Reserved */ + __I uint32_t RESERVED13; /*!< Reserved */ + __I uint32_t RESERVED14; /*!< Reserved */ + __I uint32_t RESERVED15; /*!< Reserved */ + __I uint32_t RESERVED16; /*!< Reserved */ + __I uint32_t RESERVED17; /*!< Reserved */ + __I uint32_t RESERVED18; /*!< Reserved */ + __I uint32_t RESERVED19; /*!< Reserved */ + __I uint32_t RESERVED20; /*!< Reserved */ + __I uint32_t RESERVED21; /*!< Reserved */ + __I uint32_t RESERVED22; /*!< Reserved */ + __I uint32_t RESERVED23; /*!< Reserved */ + __I uint32_t RESERVED24; /*!< Reserved */ + __I uint32_t RESERVED25; /*!< Reserved */ + __I uint32_t RESERVED26; /*!< Reserved */ + __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ + __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ + __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ + __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ + __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ + __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ + __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ + __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ + __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ + __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ + __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ + __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ + __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ + __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ + __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ + __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ + __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ + __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ + __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ + __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ + __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ + __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ + __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ + __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ + __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ + __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ + __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ + __I uint32_t TLV_END; /*!< TLV End Word */ +} TLV_Type; + +/*@}*/ /* end of group TLV */ + + +/****************************************************************************** +* WDT_A Registers +******************************************************************************/ +/** @addtogroup WDT_A MSP432P401R (WDT_A) + @{ +*/ +typedef struct { + uint16_t RESERVED0[6]; + __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ +} WDT_A_Type; + +/*@}*/ /* end of group WDT_A */ + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TI_ARM__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSP432P401R_Peripherals */ + +/****************************************************************************** +* Peripheral declaration * +******************************************************************************/ +/** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration + @{ +*/ + +#define ADC14 ((ADC14_Type *) ADC14_BASE) +#define AES256 ((AES256_Type *) AES256_BASE) +#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) +#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) +#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) +#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) +#define CRC32 ((CRC32_Type *) CRC32_BASE) +#define CS ((CS_Type *) CS_BASE) +#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) +#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) +#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) +#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) +#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) +#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) +#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) +#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) +#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) +#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) +#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) +#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) +#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) +#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) +#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) +#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) +#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) +#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) +#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) +#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) +#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) +#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) +#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) +#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) +#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) +#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) +#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) +#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) +#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) +#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) +#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) +#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) +#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) +#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) +#define FLCTL ((FLCTL_Type *) FLCTL_BASE) +#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) +#define PCM ((PCM_Type *) PCM_BASE) +#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) +#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) +#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) +#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) +#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) +#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) +#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) +#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) +#define PSS ((PSS_Type *) PSS_BASE) +#define REF_A ((REF_A_Type *) REF_A_BASE) +#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) +#define RTC_C ((RTC_C_Type *) RTC_C_BASE) +#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) +#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) +#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) +#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) +#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) +#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) +#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) +#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) +#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) +#define TLV ((TLV_Type *) TLV_BASE) +#define WDT_A ((WDT_A_Type *) WDT_A_BASE) + + +/*@}*/ /* end of group MSP432P401R_PeripheralDecl */ + +/*@}*/ /* end of group MSP432P401R_Definitions */ + +#endif /* __CMSIS_CONFIG__ */ + +/****************************************************************************** +* Peripheral register control bits * +******************************************************************************/ + +/****************************************************************************** +* ADC14 Bits +******************************************************************************/ +/* ADC14_CTL0[SC] Bits */ +#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ +#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ +/* ADC14_CTL0[ENC] Bits */ +#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ +#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ +/* ADC14_CTL0[ON] Bits */ +#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ +#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ +/* ADC14_CTL0[MSC] Bits */ +#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ +#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ +/* ADC14_CTL0[SHT0] Bits */ +#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ +#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ +#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ +#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ +#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ +#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ +#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ +#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ +#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ +#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ +#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ +#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ +#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ +#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ +#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ +#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ +#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ +#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ +#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ +#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ +#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ +#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ +/* ADC14_CTL0[SHT1] Bits */ +#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ +#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ +#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ +#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ +#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ +#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ +#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ +#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ +#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ +#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ +#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ +#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ +#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ +#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ +#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ +#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ +#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ +#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ +#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ +#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ +#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ +#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ +/* ADC14_CTL0[BUSY] Bits */ +#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ +#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ +/* ADC14_CTL0[CONSEQ] Bits */ +#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ +#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ +#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ +#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ +#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ +#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ +#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ +#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ +/* ADC14_CTL0[SSEL] Bits */ +#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ +#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ +#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ +#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ +#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ +#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ +#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ +#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ +#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ +#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ +#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ +#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ +#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ +#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ +#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ +#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ +#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ +/* ADC14_CTL0[DIV] Bits */ +#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ +#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ +#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ +#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ +#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ +#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ +#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ +#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ +#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ +#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ +#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ +#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ +#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ +#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ +#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ +#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ +#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ +#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ +#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ +#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ +#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ +/* ADC14_CTL0[ISSH] Bits */ +#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ +#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ +/* ADC14_CTL0[SHP] Bits */ +#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ +#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ +/* ADC14_CTL0[SHS] Bits */ +#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ +#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ +#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ +#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ +#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ +#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ +#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ +#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ +/* ADC14_CTL0[PDIV] Bits */ +#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ +#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ +#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ +#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ +#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ +#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ +#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ +#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ +#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ +#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ +#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ +#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ +/* ADC14_CTL1[PWRMD] Bits */ +#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ +#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ +#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ +#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ +#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ + /* up to 1 Msps. */ +#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ + /* rate must not exceed 200 ksps. */ +/* ADC14_CTL1[REFBURST] Bits */ +#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ +#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ +/* ADC14_CTL1[DF] Bits */ +#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ +#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ +/* ADC14_CTL1[RES] Bits */ +#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ +#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ +#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ +#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ +#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ +#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ +#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ +#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ +#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ +#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ +#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ +#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ +/* ADC14_CTL1[CSTARTADD] Bits */ +#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ +#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ +/* ADC14_CTL1[BATMAP] Bits */ +#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ +#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ +/* ADC14_CTL1[TCMAP] Bits */ +#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ +#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ +/* ADC14_CTL1[CH0MAP] Bits */ +#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ +#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ +/* ADC14_CTL1[CH1MAP] Bits */ +#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ +#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ +/* ADC14_CTL1[CH2MAP] Bits */ +#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ +#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ +/* ADC14_CTL1[CH3MAP] Bits */ +#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ +#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ +/* ADC14_LO0[LO0] Bits */ +#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ +#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ +/* ADC14_HI0[HI0] Bits */ +#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ +#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ +/* ADC14_LO1[LO1] Bits */ +#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ +#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ +/* ADC14_HI1[HI1] Bits */ +#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ +#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ +/* ADC14_MCTLN[INCH] Bits */ +#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ +#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ +#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ +#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ +#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ +#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ +#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ +#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ +#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ +#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ +#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ +#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ +#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ +#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ +#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ +#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ +#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ +#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ +#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ +#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ +#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ +#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ +#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ +#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ +#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ +#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ +#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ +#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ +#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ +#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ +#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ +#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ +#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ +#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ +#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ +#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ +#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ +#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ +#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ +/* ADC14_MCTLN[EOS] Bits */ +#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ +#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ +/* ADC14_MCTLN[VRSEL] Bits */ +#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ +#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ +#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ +#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ +#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ +#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ +#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ +#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ +#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ +#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ +/* ADC14_MCTLN[DIF] Bits */ +#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ +#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ +/* ADC14_MCTLN[WINC] Bits */ +#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ +#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ +/* ADC14_MCTLN[WINCTH] Bits */ +#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ +#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ +/* ADC14_MEMN[CONVRES] Bits */ +#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ +#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ +/* ADC14_IER0[IE0] Bits */ +#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ +#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ +/* ADC14_IER0[IE1] Bits */ +#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ +#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ +/* ADC14_IER0[IE2] Bits */ +#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ +#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ +/* ADC14_IER0[IE3] Bits */ +#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ +#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ +/* ADC14_IER0[IE4] Bits */ +#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ +#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ +/* ADC14_IER0[IE5] Bits */ +#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ +#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ +/* ADC14_IER0[IE6] Bits */ +#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ +#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ +/* ADC14_IER0[IE7] Bits */ +#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ +#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ +/* ADC14_IER0[IE8] Bits */ +#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ +#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ +/* ADC14_IER0[IE9] Bits */ +#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ +#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ +/* ADC14_IER0[IE10] Bits */ +#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ +#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ +/* ADC14_IER0[IE11] Bits */ +#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ +#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ +/* ADC14_IER0[IE12] Bits */ +#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ +#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ +/* ADC14_IER0[IE13] Bits */ +#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ +#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ +/* ADC14_IER0[IE14] Bits */ +#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ +#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ +/* ADC14_IER0[IE15] Bits */ +#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ +#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ +/* ADC14_IER0[IE16] Bits */ +#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ +#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ +/* ADC14_IER0[IE17] Bits */ +#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ +#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ +/* ADC14_IER0[IE19] Bits */ +#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ +#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ +/* ADC14_IER0[IE18] Bits */ +#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ +#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ +/* ADC14_IER0[IE20] Bits */ +#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ +#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ +/* ADC14_IER0[IE21] Bits */ +#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ +#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ +/* ADC14_IER0[IE22] Bits */ +#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ +#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ +/* ADC14_IER0[IE23] Bits */ +#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ +#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ +/* ADC14_IER0[IE24] Bits */ +#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ +#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE25] Bits */ +#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ +#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE26] Bits */ +#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ +#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE27] Bits */ +#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ +#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE28] Bits */ +#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ +#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE29] Bits */ +#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ +#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE30] Bits */ +#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ +#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ +/* ADC14_IER0[IE31] Bits */ +#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ +#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ +/* ADC14_IER1[INIE] Bits */ +#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ +#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ +/* ADC14_IER1[LOIE] Bits */ +#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ +#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ +/* ADC14_IER1[HIIE] Bits */ +#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ +#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ +/* ADC14_IER1[OVIE] Bits */ +#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ +#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ +/* ADC14_IER1[TOVIE] Bits */ +#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ +#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ +/* ADC14_IER1[RDYIE] Bits */ +#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ +#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ +/* ADC14_IFGR0[IFG0] Bits */ +#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ +#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ +/* ADC14_IFGR0[IFG1] Bits */ +#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ +#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ +/* ADC14_IFGR0[IFG2] Bits */ +#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ +#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ +/* ADC14_IFGR0[IFG3] Bits */ +#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ +#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ +/* ADC14_IFGR0[IFG4] Bits */ +#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ +#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ +/* ADC14_IFGR0[IFG5] Bits */ +#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ +#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ +/* ADC14_IFGR0[IFG6] Bits */ +#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ +#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ +/* ADC14_IFGR0[IFG7] Bits */ +#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ +#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ +/* ADC14_IFGR0[IFG8] Bits */ +#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ +#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ +/* ADC14_IFGR0[IFG9] Bits */ +#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ +#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ +/* ADC14_IFGR0[IFG10] Bits */ +#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ +#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ +/* ADC14_IFGR0[IFG11] Bits */ +#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ +#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ +/* ADC14_IFGR0[IFG12] Bits */ +#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ +#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ +/* ADC14_IFGR0[IFG13] Bits */ +#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ +#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ +/* ADC14_IFGR0[IFG14] Bits */ +#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ +#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ +/* ADC14_IFGR0[IFG15] Bits */ +#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ +#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ +/* ADC14_IFGR0[IFG16] Bits */ +#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ +#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ +/* ADC14_IFGR0[IFG17] Bits */ +#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ +#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ +/* ADC14_IFGR0[IFG18] Bits */ +#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ +#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ +/* ADC14_IFGR0[IFG19] Bits */ +#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ +#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ +/* ADC14_IFGR0[IFG20] Bits */ +#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ +#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ +/* ADC14_IFGR0[IFG21] Bits */ +#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ +#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ +/* ADC14_IFGR0[IFG22] Bits */ +#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ +#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ +/* ADC14_IFGR0[IFG23] Bits */ +#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ +#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ +/* ADC14_IFGR0[IFG24] Bits */ +#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ +#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ +/* ADC14_IFGR0[IFG25] Bits */ +#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ +#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ +/* ADC14_IFGR0[IFG26] Bits */ +#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ +#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ +/* ADC14_IFGR0[IFG27] Bits */ +#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ +#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ +/* ADC14_IFGR0[IFG28] Bits */ +#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ +#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ +/* ADC14_IFGR0[IFG29] Bits */ +#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ +#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ +/* ADC14_IFGR0[IFG30] Bits */ +#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ +#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ +/* ADC14_IFGR0[IFG31] Bits */ +#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ +#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ +/* ADC14_IFGR1[INIFG] Bits */ +#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ +#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ +/* ADC14_IFGR1[LOIFG] Bits */ +#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ +#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ +/* ADC14_IFGR1[HIIFG] Bits */ +#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ +#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ +/* ADC14_IFGR1[OVIFG] Bits */ +#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ +#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ +/* ADC14_IFGR1[TOVIFG] Bits */ +#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ +#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ +/* ADC14_IFGR1[RDYIFG] Bits */ +#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ +#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ +/* ADC14_CLRIFGR0[CLRIFG0] Bits */ +#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ +/* ADC14_CLRIFGR0[CLRIFG1] Bits */ +#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ +/* ADC14_CLRIFGR0[CLRIFG2] Bits */ +#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ +/* ADC14_CLRIFGR0[CLRIFG3] Bits */ +#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ +/* ADC14_CLRIFGR0[CLRIFG4] Bits */ +#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ +/* ADC14_CLRIFGR0[CLRIFG5] Bits */ +#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ +/* ADC14_CLRIFGR0[CLRIFG6] Bits */ +#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ +/* ADC14_CLRIFGR0[CLRIFG7] Bits */ +#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ +/* ADC14_CLRIFGR0[CLRIFG8] Bits */ +#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ +/* ADC14_CLRIFGR0[CLRIFG9] Bits */ +#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ +/* ADC14_CLRIFGR0[CLRIFG10] Bits */ +#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ +/* ADC14_CLRIFGR0[CLRIFG11] Bits */ +#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ +/* ADC14_CLRIFGR0[CLRIFG12] Bits */ +#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ +/* ADC14_CLRIFGR0[CLRIFG13] Bits */ +#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ +/* ADC14_CLRIFGR0[CLRIFG14] Bits */ +#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ +/* ADC14_CLRIFGR0[CLRIFG15] Bits */ +#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ +/* ADC14_CLRIFGR0[CLRIFG16] Bits */ +#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ +/* ADC14_CLRIFGR0[CLRIFG17] Bits */ +#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ +/* ADC14_CLRIFGR0[CLRIFG18] Bits */ +#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ +/* ADC14_CLRIFGR0[CLRIFG19] Bits */ +#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ +/* ADC14_CLRIFGR0[CLRIFG20] Bits */ +#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ +/* ADC14_CLRIFGR0[CLRIFG21] Bits */ +#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ +/* ADC14_CLRIFGR0[CLRIFG22] Bits */ +#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ +/* ADC14_CLRIFGR0[CLRIFG23] Bits */ +#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ +/* ADC14_CLRIFGR0[CLRIFG24] Bits */ +#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ +/* ADC14_CLRIFGR0[CLRIFG25] Bits */ +#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ +/* ADC14_CLRIFGR0[CLRIFG26] Bits */ +#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ +/* ADC14_CLRIFGR0[CLRIFG27] Bits */ +#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ +/* ADC14_CLRIFGR0[CLRIFG28] Bits */ +#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ +/* ADC14_CLRIFGR0[CLRIFG29] Bits */ +#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ +/* ADC14_CLRIFGR0[CLRIFG30] Bits */ +#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ +/* ADC14_CLRIFGR0[CLRIFG31] Bits */ +#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ +#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ +/* ADC14_CLRIFGR1[CLRINIFG] Bits */ +#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ +/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ +#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ +/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ +#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ +/* ADC14_CLRIFGR1[CLROVIFG] Bits */ +#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ +/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ +#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ +/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ +#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ +#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ + +/****************************************************************************** +* AES256 Bits +******************************************************************************/ +/* AES256_CTL0[OP] Bits */ +#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ +#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ +#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ +#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ +#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ +#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ +#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ +#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ +/* AES256_CTL0[KL] Bits */ +#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ +#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ +#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ +#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ +#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ +#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ +#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ +#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ +#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ +#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ +/* AES256_CTL0[CM] Bits */ +#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ +#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ +#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ +#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ +#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ +#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ +#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ +#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ +#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ +#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ +#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ +#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ +/* AES256_CTL0[SWRST] Bits */ +#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ +#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ +/* AES256_CTL0[RDYIFG] Bits */ +#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ +#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ +/* AES256_CTL0[ERRFG] Bits */ +#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ +#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ +/* AES256_CTL0[RDYIE] Bits */ +#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ +#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ +/* AES256_CTL0[CMEN] Bits */ +#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ +#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ +/* AES256_CTL1[BLKCNT] Bits */ +#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ +#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ +#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ +#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ +#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ +#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ +#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ +#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ +#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ +#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ +/* AES256_STAT[BUSY] Bits */ +#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ +#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ +/* AES256_STAT[KEYWR] Bits */ +#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ +#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ +/* AES256_STAT[DINWR] Bits */ +#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ +#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ +/* AES256_STAT[DOUTRD] Bits */ +#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ +#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ +/* AES256_STAT[KEYCNT] Bits */ +#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ +#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ +#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ +#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ +#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ +#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ +/* AES256_STAT[DINCNT] Bits */ +#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ +#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ +#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ +#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ +#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ +#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ +/* AES256_STAT[DOUTCNT] Bits */ +#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ +#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ +#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ +#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ +#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ +#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ +/* AES256_KEY[KEY0] Bits */ +#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ +#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ +#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ +#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ +#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ +#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ +#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ +#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ +#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ +#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ +/* AES256_KEY[KEY1] Bits */ +#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ +#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ +#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ +#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ +#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ +#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ +#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ +#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ +#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ +#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ +/* AES256_DIN[DIN0] Bits */ +#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ +#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ +#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ +#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ +#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ +#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ +#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ +#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ +#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ +#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ +/* AES256_DIN[DIN1] Bits */ +#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ +#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ +#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ +#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ +#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ +#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ +#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ +#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ +#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ +#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ +/* AES256_DOUT[DOUT0] Bits */ +#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ +#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ +#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ +#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ +#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ +#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ +#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ +#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ +#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ +#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ +/* AES256_DOUT[DOUT1] Bits */ +#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ +#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ +#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ +#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ +#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ +#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ +#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ +#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ +#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ +#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ +/* AES256_XDIN[XDIN0] Bits */ +#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ +#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ +#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ +#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ +#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ +#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ +#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ +#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ +#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ +#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ +/* AES256_XDIN[XDIN1] Bits */ +#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ +#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ +#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ +#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ +#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ +#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ +#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ +#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ +#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ +#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ +/* AES256_XIN[XIN0] Bits */ +#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ +#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ +#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ +#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ +#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ +#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ +#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ +#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ +#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ +#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ +/* AES256_XIN[XIN1] Bits */ +#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ +#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ +#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ +#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ +#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ +#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ +#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ +#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ +#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ +#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ + +/****************************************************************************** +* CAPTIO Bits +******************************************************************************/ +/* CAPTIO_CTL[PISEL] Bits */ +#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ +#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ +#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ +#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ +#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ +#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ +#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ +#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ +#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ +#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ +#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ +#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ +#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ +/* CAPTIO_CTL[POSEL] Bits */ +#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ +#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ +#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ +#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ +#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ +#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ +#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ +#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ +#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ +#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ +#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ +#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ +#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ +#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ +#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ +#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ +#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ +#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ +#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ +#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ +#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ +#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ +#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ +#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ +#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ +#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ +#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ +#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ +#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ +#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ +#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ +#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ +#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ +#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ +#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ +#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ +#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ +#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ +/* CAPTIO_CTL[EN] Bits */ +#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ +#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ +/* CAPTIO_CTL[STATE] Bits */ +#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ +#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ + +/****************************************************************************** +* COMP_E Bits +******************************************************************************/ +/* COMP_E_CTL0[IPSEL] Bits */ +#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ +#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ +#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ +#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ +#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ +#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ +#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ +#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ +#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ +#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ +#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ +#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ +#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ +#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ +#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ +#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ +#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ +#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ +#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ +#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ +#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ +#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ +/* COMP_E_CTL0[IPEN] Bits */ +#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ +#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ +/* COMP_E_CTL0[IMSEL] Bits */ +#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ +#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ +#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ +#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ +#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ +#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ +#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ +#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ +#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ +#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ +#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ +#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ +#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ +#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ +#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ +#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ +#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ +#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ +#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ +#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ +#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ +#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ +/* COMP_E_CTL0[IMEN] Bits */ +#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ +#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ +/* COMP_E_CTL1[OUT] Bits */ +#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ +#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ +/* COMP_E_CTL1[OUTPOL] Bits */ +#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ +#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ +/* COMP_E_CTL1[F] Bits */ +#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ +#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ +/* COMP_E_CTL1[IES] Bits */ +#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ +#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ +/* COMP_E_CTL1[SHORT] Bits */ +#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ +#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ +/* COMP_E_CTL1[EX] Bits */ +#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ +#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ +/* COMP_E_CTL1[FDLY] Bits */ +#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ +#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ +#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ +#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ +#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ +#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ +#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ +#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ +/* COMP_E_CTL1[PWRMD] Bits */ +#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ +#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ +#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ +#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ +#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ +#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ +#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ +/* COMP_E_CTL1[ON] Bits */ +#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ +#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ +/* COMP_E_CTL1[MRVL] Bits */ +#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ +#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ +/* COMP_E_CTL1[MRVS] Bits */ +#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ +#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) +/* COMP_E_CTL2[REF0] Bits */ +#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ +#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ +#define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ +#define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ +#define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ +#define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ +#define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ +#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ +#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ +#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ +#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ +#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ +#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ +#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ +#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ +#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ +#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ +#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ +#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ +#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ +#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ +#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ +#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ +#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ +#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ +#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ +#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ +#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ +#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ +#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ +#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ +#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ +#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ +#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ +#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ +#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ +#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ +#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ +#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ +/* COMP_E_CTL2[RSEL] Bits */ +#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ +#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ +/* COMP_E_CTL2[RS] Bits */ +#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ +#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ +#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ +#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ +#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ +#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ +#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ +#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ +/* COMP_E_CTL2[REF1] Bits */ +#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ +#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ +#define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ +#define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ +#define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ +#define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ +#define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ +#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ +#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ +#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ +#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ +#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ +#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ +#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ +#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ +#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ +#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ +#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ +#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ +#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ +#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ +#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ +#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ +#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ +#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ +#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ +#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ +#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ +#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ +#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ +#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ +#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ +#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ +#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ +#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ +#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ +#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ +#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ +#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ +/* COMP_E_CTL2[REFL] Bits */ +#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ +#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ +#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ +#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ +#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ +#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ +#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ +#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ +#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ +#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ +#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ +#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ +/* COMP_E_CTL2[REFACC] Bits */ +#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ +#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ +/* COMP_E_CTL3[PD0] Bits */ +#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ +#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ +/* COMP_E_CTL3[PD1] Bits */ +#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ +#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ +/* COMP_E_CTL3[PD2] Bits */ +#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ +#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ +/* COMP_E_CTL3[PD3] Bits */ +#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ +#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ +/* COMP_E_CTL3[PD4] Bits */ +#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ +#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ +/* COMP_E_CTL3[PD5] Bits */ +#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ +#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ +/* COMP_E_CTL3[PD6] Bits */ +#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ +#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ +/* COMP_E_CTL3[PD7] Bits */ +#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ +#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ +/* COMP_E_CTL3[PD8] Bits */ +#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ +#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ +/* COMP_E_CTL3[PD9] Bits */ +#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ +#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ +/* COMP_E_CTL3[PD10] Bits */ +#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ +#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ +/* COMP_E_CTL3[PD11] Bits */ +#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ +#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ +/* COMP_E_CTL3[PD12] Bits */ +#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ +#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ +/* COMP_E_CTL3[PD13] Bits */ +#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ +#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ +/* COMP_E_CTL3[PD14] Bits */ +#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ +#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ +/* COMP_E_CTL3[PD15] Bits */ +#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ +#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ +/* COMP_E_INT[IFG] Bits */ +#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ +#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ +/* COMP_E_INT[IIFG] Bits */ +#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ +#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ +/* COMP_E_INT[RDYIFG] Bits */ +#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ +#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ +/* COMP_E_INT[IE] Bits */ +#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ +#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ +/* COMP_E_INT[IIE] Bits */ +#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ +#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ +/* COMP_E_INT[RDYIE] Bits */ +#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ +#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ + +/****************************************************************************** +* COREDEBUG Bits +******************************************************************************/ + + +/****************************************************************************** +* CRC32 Bits +******************************************************************************/ + +/****************************************************************************** +* CS Bits +******************************************************************************/ +/* CS_KEY[KEY] Bits */ +#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ +#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ +/* CS_CTL0[DCOTUNE] Bits */ +#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ +#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ +/* CS_CTL0[DCORSEL] Bits */ +#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ +#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ +#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ +#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ +#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ +#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ +#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ +#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ +#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ +#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ +#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ +/* CS_CTL0[DCORES] Bits */ +#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ +#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ +/* CS_CTL0[DCOEN] Bits */ +#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ +#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ +/* CS_CTL1[SELM] Bits */ +#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ +#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ +#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ +#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ +#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ +#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) +#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) +#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) +#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) +#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ +#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ +#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) +#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) +#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) +#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) +#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ +#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ +/* CS_CTL1[SELS] Bits */ +#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ +#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ +#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ +#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ +#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ +#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) +#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) +#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) +#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) +#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ +#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ +#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) +#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) +#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) +#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) +#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ +#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ +/* CS_CTL1[SELA] Bits */ +#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ +#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ +#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ +#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ +#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ +#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) +#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) +#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ +#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) +#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) +/* CS_CTL1[SELB] Bits */ +#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ +#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ +/* CS_CTL1[DIVM] Bits */ +#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ +#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ +#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ +#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ +#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ +#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ +#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ +#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ +#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ +#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ +#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ +#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ +#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ +#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ +#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ +#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ +#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ +#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ +#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ +#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ +#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ +/* CS_CTL1[DIVHS] Bits */ +#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ +#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ +#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ +#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ +#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ +#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ +#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ +#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ +#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ +#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ +#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ +#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ +#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ +#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ +#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ +#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ +#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ +#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ +#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ +#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ +#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ +/* CS_CTL1[DIVA] Bits */ +#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ +#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ +#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ +#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ +#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ +#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ +#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ +#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ +#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ +#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ +#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ +#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ +#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ +#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ +#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ +#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ +#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ +#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ +#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ +#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ +#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ +/* CS_CTL1[DIVS] Bits */ +#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ +#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ +#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ +#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ +#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ +#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ +#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ +#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ +#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ +#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ +#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ +#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ +#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ +#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ +#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ +#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ +#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ +#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ +#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ +#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ +#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ +/* CS_CTL2[LFXTDRIVE] Bits */ +#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ +#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ +#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ +#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ +#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ +#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ +#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ +#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ +/* CS_CTL2[LFXT_EN] Bits */ +#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ +#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ +/* CS_CTL2[LFXTBYPASS] Bits */ +#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ +#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ +/* CS_CTL2[HFXTDRIVE] Bits */ +#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ +#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ +/* CS_CTL2[HFXTFREQ] Bits */ +#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ +#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ +#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ +#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ +#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ +#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ +#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ +#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ +#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ +#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ +#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ +#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ +#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ +/* CS_CTL2[HFXT_EN] Bits */ +#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ +#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ +/* CS_CTL2[HFXTBYPASS] Bits */ +#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ +#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ +/* CS_CTL3[FCNTLF] Bits */ +#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ +#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ +#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ +#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ +#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ +#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ +#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ +#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ +#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ +#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ +#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ +#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ +/* CS_CTL3[RFCNTLF] Bits */ +#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ +#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ +/* CS_CTL3[FCNTLF_EN] Bits */ +#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ +#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ +/* CS_CTL3[FCNTHF] Bits */ +#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ +#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ +#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ +#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ +#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ +#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ +#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ +#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ +#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ +#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ +#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ +#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ +/* CS_CTL3[RFCNTHF] Bits */ +#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ +#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ +/* CS_CTL3[FCNTHF_EN] Bits */ +#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ +#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ +/* CS_CLKEN[ACLK_EN] Bits */ +#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ +#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ +/* CS_CLKEN[MCLK_EN] Bits */ +#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ +#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ +/* CS_CLKEN[HSMCLK_EN] Bits */ +#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ +#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ +/* CS_CLKEN[SMCLK_EN] Bits */ +#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ +#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ +/* CS_CLKEN[VLO_EN] Bits */ +#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ +#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ +/* CS_CLKEN[REFO_EN] Bits */ +#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ +#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ +/* CS_CLKEN[MODOSC_EN] Bits */ +#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ +#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ +/* CS_CLKEN[REFOFSEL] Bits */ +#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ +#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ +/* CS_STAT[DCO_ON] Bits */ +#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ +#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ +/* CS_STAT[DCOBIAS_ON] Bits */ +#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ +#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ +/* CS_STAT[HFXT_ON] Bits */ +#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ +#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ +/* CS_STAT[MODOSC_ON] Bits */ +#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ +#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ +/* CS_STAT[VLO_ON] Bits */ +#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ +#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ +/* CS_STAT[LFXT_ON] Bits */ +#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ +#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ +/* CS_STAT[REFO_ON] Bits */ +#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ +#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ +/* CS_STAT[ACLK_ON] Bits */ +#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ +#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ +/* CS_STAT[MCLK_ON] Bits */ +#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ +#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ +/* CS_STAT[HSMCLK_ON] Bits */ +#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ +#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ +/* CS_STAT[SMCLK_ON] Bits */ +#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ +#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ +/* CS_STAT[MODCLK_ON] Bits */ +#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ +#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ +/* CS_STAT[VLOCLK_ON] Bits */ +#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ +#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ +/* CS_STAT[LFXTCLK_ON] Bits */ +#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ +#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ +/* CS_STAT[REFOCLK_ON] Bits */ +#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ +#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ +/* CS_STAT[ACLK_READY] Bits */ +#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ +#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ +/* CS_STAT[MCLK_READY] Bits */ +#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ +#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ +/* CS_STAT[HSMCLK_READY] Bits */ +#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ +#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ +/* CS_STAT[SMCLK_READY] Bits */ +#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ +#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ +/* CS_STAT[BCLK_READY] Bits */ +#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ +#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ +/* CS_IE[LFXTIE] Bits */ +#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ +#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ +/* CS_IE[HFXTIE] Bits */ +#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ +#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ +/* CS_IE[DCOR_OPNIE] Bits */ +#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ +#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ +/* CS_IE[FCNTLFIE] Bits */ +#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ +#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ +/* CS_IE[FCNTHFIE] Bits */ +#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ +#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ +/* CS_IFG[LFXTIFG] Bits */ +#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ +#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ +/* CS_IFG[HFXTIFG] Bits */ +#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ +#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ +/* CS_IFG[DCOR_SHTIFG] Bits */ +#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ +#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ +/* CS_IFG[DCOR_OPNIFG] Bits */ +#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ +#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ +/* CS_IFG[FCNTLFIFG] Bits */ +#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ +#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ +/* CS_IFG[FCNTHFIFG] Bits */ +#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ +#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ +/* CS_CLRIFG[CLR_LFXTIFG] Bits */ +#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ +#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ +/* CS_CLRIFG[CLR_HFXTIFG] Bits */ +#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ +#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ +/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ +#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ +#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ +/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ +#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ +#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ +/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ +#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ +#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ +/* CS_SETIFG[SET_LFXTIFG] Bits */ +#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ +#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ +/* CS_SETIFG[SET_HFXTIFG] Bits */ +#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ +#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ +/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ +#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ +#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ +/* CS_SETIFG[SET_FCNTHFIFG] Bits */ +#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ +#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ +/* CS_SETIFG[SET_FCNTLFIFG] Bits */ +#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ +#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ +/* CS_DCOERCAL0[DCO_TCCAL] Bits */ +#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ +#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ +/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ +#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ +#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ +/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ +#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ +#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ +/* Pre-defined bitfield values */ +#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ + +/****************************************************************************** +* DIO Bits +******************************************************************************/ +/* DIO_IV[IV] Bits */ +#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ +#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ +#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ +#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ +#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ +#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ +#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ +#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ +#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ + /* Priority: Highest */ +#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ +#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ +#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ +#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ +#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ +#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ +#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ + /* Priority: Lowest */ +#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ +#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ + /* Priority: Highest */ +#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ +#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ +#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ +#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ +#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ +#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ +#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ + /* Priority: Lowest */ + + +/****************************************************************************** +* DMA Bits +******************************************************************************/ +/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ +#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ +#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ +/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ +#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ +#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ +/* DMA_SW_CHTRIG[CH0] Bits */ +#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ +#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ +/* DMA_SW_CHTRIG[CH1] Bits */ +#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ +#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ +/* DMA_SW_CHTRIG[CH2] Bits */ +#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ +#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ +/* DMA_SW_CHTRIG[CH3] Bits */ +#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ +#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ +/* DMA_SW_CHTRIG[CH4] Bits */ +#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ +#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ +/* DMA_SW_CHTRIG[CH5] Bits */ +#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ +#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ +/* DMA_SW_CHTRIG[CH6] Bits */ +#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ +#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ +/* DMA_SW_CHTRIG[CH7] Bits */ +#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ +#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ +/* DMA_SW_CHTRIG[CH8] Bits */ +#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ +#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ +/* DMA_SW_CHTRIG[CH9] Bits */ +#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ +#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ +/* DMA_SW_CHTRIG[CH10] Bits */ +#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ +#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ +/* DMA_SW_CHTRIG[CH11] Bits */ +#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ +#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ +/* DMA_SW_CHTRIG[CH12] Bits */ +#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ +#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ +/* DMA_SW_CHTRIG[CH13] Bits */ +#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ +#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ +/* DMA_SW_CHTRIG[CH14] Bits */ +#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ +#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ +/* DMA_SW_CHTRIG[CH15] Bits */ +#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ +#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ +/* DMA_SW_CHTRIG[CH16] Bits */ +#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ +#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ +/* DMA_SW_CHTRIG[CH17] Bits */ +#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ +#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ +/* DMA_SW_CHTRIG[CH18] Bits */ +#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ +#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ +/* DMA_SW_CHTRIG[CH19] Bits */ +#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ +#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ +/* DMA_SW_CHTRIG[CH20] Bits */ +#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ +#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ +/* DMA_SW_CHTRIG[CH21] Bits */ +#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ +#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ +/* DMA_SW_CHTRIG[CH22] Bits */ +#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ +#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ +/* DMA_SW_CHTRIG[CH23] Bits */ +#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ +#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ +/* DMA_SW_CHTRIG[CH24] Bits */ +#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ +#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ +/* DMA_SW_CHTRIG[CH25] Bits */ +#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ +#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ +/* DMA_SW_CHTRIG[CH26] Bits */ +#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ +#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ +/* DMA_SW_CHTRIG[CH27] Bits */ +#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ +#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ +/* DMA_SW_CHTRIG[CH28] Bits */ +#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ +#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ +/* DMA_SW_CHTRIG[CH29] Bits */ +#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ +#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ +/* DMA_SW_CHTRIG[CH30] Bits */ +#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ +#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ +/* DMA_SW_CHTRIG[CH31] Bits */ +#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ +#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ +/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ +#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ +#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ +/* DMA_INT1_SRCCFG[INT_SRC] Bits */ +#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ +#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ +/* DMA_INT1_SRCCFG[EN] Bits */ +#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ +#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ +/* DMA_INT2_SRCCFG[INT_SRC] Bits */ +#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ +#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ +/* DMA_INT2_SRCCFG[EN] Bits */ +#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ +#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ +/* DMA_INT3_SRCCFG[INT_SRC] Bits */ +#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ +#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ +/* DMA_INT3_SRCCFG[EN] Bits */ +#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ +#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ +/* DMA_INT0_SRCFLG[CH0] Bits */ +#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ +#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH1] Bits */ +#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ +#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH2] Bits */ +#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ +#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH3] Bits */ +#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ +#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH4] Bits */ +#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ +#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH5] Bits */ +#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ +#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH6] Bits */ +#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ +#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH7] Bits */ +#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ +#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH8] Bits */ +#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ +#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH9] Bits */ +#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ +#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH10] Bits */ +#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ +#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH11] Bits */ +#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ +#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH12] Bits */ +#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ +#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH13] Bits */ +#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ +#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH14] Bits */ +#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ +#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH15] Bits */ +#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ +#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH16] Bits */ +#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ +#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH17] Bits */ +#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ +#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH18] Bits */ +#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ +#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH19] Bits */ +#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ +#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH20] Bits */ +#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ +#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH21] Bits */ +#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ +#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH22] Bits */ +#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ +#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH23] Bits */ +#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ +#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH24] Bits */ +#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ +#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH25] Bits */ +#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ +#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH26] Bits */ +#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ +#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH27] Bits */ +#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ +#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH28] Bits */ +#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ +#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH29] Bits */ +#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ +#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH30] Bits */ +#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ +#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ +/* DMA_INT0_SRCFLG[CH31] Bits */ +#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ +#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ +/* DMA_INT0_CLRFLG[CH0] Bits */ +#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ +#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH1] Bits */ +#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ +#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH2] Bits */ +#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ +#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH3] Bits */ +#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ +#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH4] Bits */ +#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ +#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH5] Bits */ +#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ +#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH6] Bits */ +#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ +#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH7] Bits */ +#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ +#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH8] Bits */ +#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ +#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH9] Bits */ +#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ +#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH10] Bits */ +#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ +#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH11] Bits */ +#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ +#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH12] Bits */ +#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ +#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH13] Bits */ +#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ +#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH14] Bits */ +#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ +#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH15] Bits */ +#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ +#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH16] Bits */ +#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ +#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH17] Bits */ +#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ +#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH18] Bits */ +#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ +#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH19] Bits */ +#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ +#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH20] Bits */ +#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ +#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH21] Bits */ +#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ +#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH22] Bits */ +#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ +#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH23] Bits */ +#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ +#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH24] Bits */ +#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ +#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH25] Bits */ +#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ +#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH26] Bits */ +#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ +#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH27] Bits */ +#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ +#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH28] Bits */ +#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ +#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH29] Bits */ +#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ +#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH30] Bits */ +#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ +#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_INT0_CLRFLG[CH31] Bits */ +#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ +#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ +/* DMA_STAT[MASTEN] Bits */ +#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ +#define DMA_STAT_MASTEN ((uint32_t)0x00000001) +/* DMA_STAT[STATE] Bits */ +#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ +#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ +#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ +#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ +#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ +#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ +#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ +#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ +#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ +#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ +#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ +#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ +#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ +#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ +#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ +#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ +#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ +#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ +#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ +#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ +#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ +#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ +/* DMA_STAT[DMACHANS] Bits */ +#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ +#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ +#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ +#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ +#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ +#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ +#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ +#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ +#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ +#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ +#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ +/* DMA_STAT[TESTSTAT] Bits */ +#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ +#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ +#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ +#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ +#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ +#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ +#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ +#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ +/* DMA_CFG[MASTEN] Bits */ +#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ +#define DMA_CFG_MASTEN ((uint32_t)0x00000001) +/* DMA_CFG[CHPROTCTRL] Bits */ +#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ +#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ +/* DMA_CTLBASE[ADDR] Bits */ +#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ +#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ +/* DMA_ERRCLR[ERRCLR] Bits */ +#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ +#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) +/* DMA channel definitions and memory structure alignment */ +#define __MCU_NUM_DMA_CHANNELS__ 8 +#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 +#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) + +/* UDMA_STAT Control Bits */ +#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ +#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ +#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ +#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ +#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ +#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ +#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ +#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ +#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ +#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ +#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ +#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ +#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ +#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ +#define UDMA_STAT_DMACHANS_S (16) + +/* UDMA_CFG Control Bits */ +#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ + +/* UDMA_CTLBASE Control Bits */ +#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ +#define UDMA_CTLBASE_ADDR_S (10) + +/* UDMA_ALTBASE Control Bits */ +#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ +#define UDMA_ALTBASE_ADDR_S ( 0) + +/* UDMA_WAITSTAT Control Bits */ +#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ + +/* UDMA_SWREQ Control Bits */ +#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ + +/* UDMA_USEBURSTSET Control Bits */ +#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ + +/* UDMA_USEBURSTCLR Control Bits */ +#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ + +/* UDMA_REQMASKSET Control Bits */ +#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ + +/* UDMA_REQMASKCLR Control Bits */ +#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ + +/* UDMA_ENASET Control Bits */ +#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ + +/* UDMA_ENACLR Control Bits */ +#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ + +/* UDMA_ALTSET Control Bits */ +#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ + +/* UDMA_ALTCLR Control Bits */ +#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ + +/* UDMA_PRIOSET Control Bits */ +#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ + +/* UDMA_PRIOCLR Control Bits */ +#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ + +/* UDMA_ERRCLR Control Bits */ +#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ + +/* UDMA_CHASGN Control Bits */ +#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ +#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ +#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ + +/* Micro Direct Memory Access (uDMA) offsets */ +#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ +#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ +#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ + +/* UDMA_O_SRCENDP Control Bits */ +#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ +#define UDMA_SRCENDP_ADDR_S ( 0) + +/* UDMA_O_DSTENDP Control Bits */ +#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ +#define UDMA_DSTENDP_ADDR_S ( 0) + +/* UDMA_O_CHCTL Control Bits */ +#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ +#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ +#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ +#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ +#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ +#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ +#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ +#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ +#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ +#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ +#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ +#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ +#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ +#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ +#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ +#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ +#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ +#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ +#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ +#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ +#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ +#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ +#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ +#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ +#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ +#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ +#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ +#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ +#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ +#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ +#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ +#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ +#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ +#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ +#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ +#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ +#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ +#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ +#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ +#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ +#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ + +#define UDMA_CHCTL_XFERSIZE_S ( 4) + + +/****************************************************************************** +* DWT Bits +******************************************************************************/ + + +/****************************************************************************** +* EUSCI_A Bits +******************************************************************************/ +/* EUSCI_A_CTLW0[SWRST] Bits */ +#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ +#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ +/* EUSCI_A_CTLW0[TXBRK] Bits */ +#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ +#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ +/* EUSCI_A_CTLW0[TXADDR] Bits */ +#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ +#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ +/* EUSCI_A_CTLW0[DORM] Bits */ +#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ +#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ +/* EUSCI_A_CTLW0[BRKIE] Bits */ +#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ +#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ +/* EUSCI_A_CTLW0[RXEIE] Bits */ +#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ +#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ +/* EUSCI_A_CTLW0[SSEL] Bits */ +#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ +#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ +#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ +#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ +#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ +#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ +#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ +#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ +#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ +#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ +/* EUSCI_A_CTLW0[SYNC] Bits */ +#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ +#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ +/* EUSCI_A_CTLW0[MODE] Bits */ +#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ +#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ +#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ +#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ +#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ +#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ +#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ +#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ +/* EUSCI_A_CTLW0[SPB] Bits */ +#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ +#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ +/* EUSCI_A_CTLW0[SEVENBIT] Bits */ +#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ +#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ +/* EUSCI_A_CTLW0[MSB] Bits */ +#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ +#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ +/* EUSCI_A_CTLW0[PAR] Bits */ +#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ +#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ +/* EUSCI_A_CTLW0[PEN] Bits */ +#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ +#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ +/* EUSCI_A_CTLW0[STEM] Bits */ +#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ +#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ +/* EUSCI_A_CTLW0[MST] Bits */ +#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ +#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ +/* EUSCI_A_CTLW0[CKPL] Bits */ +#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ +#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ +/* EUSCI_A_CTLW0[CKPH] Bits */ +#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ +#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ +/* EUSCI_A_CTLW1[GLIT] Bits */ +#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ +#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ +#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ +#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ +#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ +#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ +#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ +#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ +/* EUSCI_A_MCTLW[OS16] Bits */ +#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ +#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ +/* EUSCI_A_MCTLW[BRF] Bits */ +#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ +#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ +/* EUSCI_A_MCTLW[BRS] Bits */ +#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ +#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ +/* EUSCI_A_STATW[BUSY] Bits */ +#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ +#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ +/* EUSCI_A_STATW[ADDR_IDLE] Bits */ +#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ +#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ +/* EUSCI_A_STATW[RXERR] Bits */ +#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ +#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ +/* EUSCI_A_STATW[BRK] Bits */ +#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ +#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ +/* EUSCI_A_STATW[PE] Bits */ +#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ +#define EUSCI_A_STATW_PE ((uint16_t)0x0010) +/* EUSCI_A_STATW[OE] Bits */ +#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ +#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ +/* EUSCI_A_STATW[FE] Bits */ +#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ +#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ +/* EUSCI_A_STATW[LISTEN] Bits */ +#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ +#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ +/* EUSCI_A_STATW[SPI_BUSY] Bits */ +#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ +#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ +/* EUSCI_A_RXBUF[RXBUF] Bits */ +#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ +#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ +/* EUSCI_A_TXBUF[TXBUF] Bits */ +#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ +#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ +/* EUSCI_A_ABCTL[ABDEN] Bits */ +#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ +#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ +/* EUSCI_A_ABCTL[BTOE] Bits */ +#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ +#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ +/* EUSCI_A_ABCTL[STOE] Bits */ +#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ +#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ +/* EUSCI_A_ABCTL[DELIM] Bits */ +#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ +#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ +#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ +#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ +#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ +#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ +#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ +#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ +/* EUSCI_A_IRCTL[IREN] Bits */ +#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ +#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ +/* EUSCI_A_IRCTL[IRTXCLK] Bits */ +#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ +#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ +/* EUSCI_A_IRCTL[IRTXPL] Bits */ +#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ +#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ +/* EUSCI_A_IRCTL[IRRXFE] Bits */ +#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ +#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ +/* EUSCI_A_IRCTL[IRRXPL] Bits */ +#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ +#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ +/* EUSCI_A_IRCTL[IRRXFL] Bits */ +#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ +#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ +/* EUSCI_A_IE[RXIE] Bits */ +#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ +#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ +/* EUSCI_A_IE[TXIE] Bits */ +#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ +#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ +/* EUSCI_A_IE[STTIE] Bits */ +#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ +#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ +/* EUSCI_A_IE[TXCPTIE] Bits */ +#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ +#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ +/* EUSCI_A_IFG[RXIFG] Bits */ +#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ +#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ +/* EUSCI_A_IFG[TXIFG] Bits */ +#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ +#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ +/* EUSCI_A_IFG[STTIFG] Bits */ +#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ +#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ +/* EUSCI_A_IFG[TXCPTIFG] Bits */ +#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ +#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ +/* legacy definitions for backward compatibility to version 2100 */ +#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ +#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ +#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ +#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ + + +/****************************************************************************** +* EUSCI_B Bits +******************************************************************************/ +/* EUSCI_B_CTLW0[SWRST] Bits */ +#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ +#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ +/* EUSCI_B_CTLW0[TXSTT] Bits */ +#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ +#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ +/* EUSCI_B_CTLW0[TXSTP] Bits */ +#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ +#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ +/* EUSCI_B_CTLW0[TXNACK] Bits */ +#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ +#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ +/* EUSCI_B_CTLW0[TR] Bits */ +#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ +#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ +/* EUSCI_B_CTLW0[TXACK] Bits */ +#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ +#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ +/* EUSCI_B_CTLW0[SSEL] Bits */ +#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ +#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ +#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ +#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ +#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ +#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ +#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ +#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ +#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ +#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ +#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ +/* EUSCI_B_CTLW0[SYNC] Bits */ +#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ +#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ +/* EUSCI_B_CTLW0[MODE] Bits */ +#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ +#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ +#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ +#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ +#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ +#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ +#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ +#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ +/* EUSCI_B_CTLW0[MST] Bits */ +#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ +#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ +/* EUSCI_B_CTLW0[MM] Bits */ +#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ +#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ +/* EUSCI_B_CTLW0[SLA10] Bits */ +#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ +#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ +/* EUSCI_B_CTLW0[A10] Bits */ +#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ +#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ +/* EUSCI_B_CTLW0[STEM] Bits */ +#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ +#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ +/* EUSCI_B_CTLW0[SEVENBIT] Bits */ +#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ +#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ +/* EUSCI_B_CTLW0[MSB] Bits */ +#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ +#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ +/* EUSCI_B_CTLW0[CKPL] Bits */ +#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ +#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ +/* EUSCI_B_CTLW0[CKPH] Bits */ +#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ +#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ +/* EUSCI_B_CTLW1[GLIT] Bits */ +#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ +#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ +#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ +#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ +#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ +#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ +#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ +#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ +/* EUSCI_B_CTLW1[ASTP] Bits */ +#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ +#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ +#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ +#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ +#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ + /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ +#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ + /* UCBxTBCNT */ +#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ + /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ + /* threshold */ +/* EUSCI_B_CTLW1[SWACK] Bits */ +#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ +#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ +/* EUSCI_B_CTLW1[STPNACK] Bits */ +#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ +#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ +/* EUSCI_B_CTLW1[CLTO] Bits */ +#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ +#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ +#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ +#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ +#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ +#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ +#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ +#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ +/* EUSCI_B_CTLW1[ETXINT] Bits */ +#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ +#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ +/* EUSCI_B_STATW[BBUSY] Bits */ +#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ +#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ +/* EUSCI_B_STATW[GC] Bits */ +#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ +#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ +/* EUSCI_B_STATW[SCLLOW] Bits */ +#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ +#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ +/* EUSCI_B_STATW[BCNT] Bits */ +#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ +#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ +/* EUSCI_B_STATW[SPI_BUSY] Bits */ +#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ +#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ +/* EUSCI_B_STATW[OE] Bits */ +#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ +#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ +/* EUSCI_B_STATW[FE] Bits */ +#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ +#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ +/* EUSCI_B_STATW[LISTEN] Bits */ +#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ +#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ +/* EUSCI_B_TBCNT[TBCNT] Bits */ +#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ +#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ +/* EUSCI_B_RXBUF[RXBUF] Bits */ +#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ +#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ +/* EUSCI_B_TXBUF[TXBUF] Bits */ +#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ +#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ +/* EUSCI_B_I2COA0[I2COA0] Bits */ +#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ +#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ +/* EUSCI_B_I2COA0[OAEN] Bits */ +#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ +#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ +/* EUSCI_B_I2COA0[GCEN] Bits */ +#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ +#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ +/* EUSCI_B_I2COA1[I2COA1] Bits */ +#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ +#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ +/* EUSCI_B_I2COA1[OAEN] Bits */ +#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ +#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ +/* EUSCI_B_I2COA2[I2COA2] Bits */ +#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ +#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ +/* EUSCI_B_I2COA2[OAEN] Bits */ +#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ +#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ +/* EUSCI_B_I2COA3[I2COA3] Bits */ +#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ +#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ +/* EUSCI_B_I2COA3[OAEN] Bits */ +#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ +#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ +/* EUSCI_B_ADDRX[ADDRX] Bits */ +#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ +#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ +#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ +#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ +#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ +#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ +#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ +#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ +#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ +#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ +#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ +#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ +/* EUSCI_B_ADDMASK[ADDMASK] Bits */ +#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ +#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ +/* EUSCI_B_I2CSA[I2CSA] Bits */ +#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ +#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ +/* EUSCI_B_IE[RXIE0] Bits */ +#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ +#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ +/* EUSCI_B_IE[TXIE0] Bits */ +#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ +#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ +/* EUSCI_B_IE[STTIE] Bits */ +#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ +#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ +/* EUSCI_B_IE[STPIE] Bits */ +#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ +#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ +/* EUSCI_B_IE[ALIE] Bits */ +#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ +#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ +/* EUSCI_B_IE[NACKIE] Bits */ +#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ +#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ +/* EUSCI_B_IE[BCNTIE] Bits */ +#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ +#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ +/* EUSCI_B_IE[CLTOIE] Bits */ +#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ +#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ +/* EUSCI_B_IE[RXIE1] Bits */ +#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ +#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ +/* EUSCI_B_IE[TXIE1] Bits */ +#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ +#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ +/* EUSCI_B_IE[RXIE2] Bits */ +#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ +#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ +/* EUSCI_B_IE[TXIE2] Bits */ +#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ +#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ +/* EUSCI_B_IE[RXIE3] Bits */ +#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ +#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ +/* EUSCI_B_IE[TXIE3] Bits */ +#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ +#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ +/* EUSCI_B_IE[BIT9IE] Bits */ +#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ +#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ +/* EUSCI_B_IE[RXIE] Bits */ +#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ +#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ +/* EUSCI_B_IE[TXIE] Bits */ +#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ +#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ +/* EUSCI_B_IFG[RXIFG0] Bits */ +#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ +#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ +/* EUSCI_B_IFG[TXIFG0] Bits */ +#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ +#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ +/* EUSCI_B_IFG[STTIFG] Bits */ +#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ +#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ +/* EUSCI_B_IFG[STPIFG] Bits */ +#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ +#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ +/* EUSCI_B_IFG[ALIFG] Bits */ +#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ +#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ +/* EUSCI_B_IFG[NACKIFG] Bits */ +#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ +#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ +/* EUSCI_B_IFG[BCNTIFG] Bits */ +#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ +#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ +/* EUSCI_B_IFG[CLTOIFG] Bits */ +#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ +#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ +/* EUSCI_B_IFG[RXIFG1] Bits */ +#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ +#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ +/* EUSCI_B_IFG[TXIFG1] Bits */ +#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ +#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ +/* EUSCI_B_IFG[RXIFG2] Bits */ +#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ +#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ +/* EUSCI_B_IFG[TXIFG2] Bits */ +#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ +#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ +/* EUSCI_B_IFG[RXIFG3] Bits */ +#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ +#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ +/* EUSCI_B_IFG[TXIFG3] Bits */ +#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ +#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ +/* EUSCI_B_IFG[BIT9IFG] Bits */ +#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ +#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ +/* EUSCI_B_IFG[RXIFG] Bits */ +#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ +#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ +/* EUSCI_B_IFG[TXIFG] Bits */ +#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ +#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ +/* legacy definitions for backward compatibility to version 2100 */ +#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ +#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ +#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ +#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ + + +/****************************************************************************** +* FLCTL Bits +******************************************************************************/ +/* FLCTL_POWER_STAT[PSTAT] Bits */ +#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ +#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ +#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ +#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ +#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ +#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ +#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ +#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ +#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ +#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ +#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ +#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ +#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ +/* FLCTL_POWER_STAT[LDOSTAT] Bits */ +#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ +#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ +/* FLCTL_POWER_STAT[VREFSTAT] Bits */ +#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ +#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ +/* FLCTL_POWER_STAT[IREFSTAT] Bits */ +#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ +#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ +/* FLCTL_POWER_STAT[TRIMSTAT] Bits */ +#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ +#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ +/* FLCTL_POWER_STAT[RD_2T] Bits */ +#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ +#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ +/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ +#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ +#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ +#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ +#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ +#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ +#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ +#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ +#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ +/* FLCTL_BANK0_RDCTL[BUFI] Bits */ +#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ +#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ +/* FLCTL_BANK0_RDCTL[BUFD] Bits */ +#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ +#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ +/* FLCTL_BANK0_RDCTL[WAIT] Bits */ +#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ +#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ +#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ +#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ +#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ +#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ +#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ +#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ +/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ +#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ +/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ +#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ +#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ +#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ +#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ +#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ +#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ +#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ +#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ +/* FLCTL_BANK1_RDCTL[BUFI] Bits */ +#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ +#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ +/* FLCTL_BANK1_RDCTL[BUFD] Bits */ +#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ +#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ +/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ +#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ +/* FLCTL_BANK1_RDCTL[WAIT] Bits */ +#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ +#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ +#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ +#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ +#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ +#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ +#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ +#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ +/* FLCTL_RDBRST_CTLSTAT[START] Bits */ +#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ +/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ +#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ +/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ +#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ +/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ +#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ +/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ +#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ +/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ +#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ + /* explicitly cleared by SW) */ +/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ +#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ +/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ +#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ +/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ +#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ +#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ +/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ +#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ +#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ +/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ +#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ +#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ +/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ +#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ +#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ +/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ +#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ +#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ +/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ +#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ +#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ +/* FLCTL_PRG_CTLSTAT[MODE] Bits */ +#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ +#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ +/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ +#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ +#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ +/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ +#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ +#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ +/* FLCTL_PRG_CTLSTAT[STATUS] Bits */ +#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ +#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ +#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ +#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ +#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ +#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ +#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ +#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ +/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ +#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ +#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ +/* FLCTL_PRGBRST_CTLSTAT[START] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ +/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ +#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ +/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ +#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ +#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ +#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ + /* FLCTL_PRGBRST_STARTADDR Register */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ + /* Register */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ + /* Register */ +#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ + /* Register */ +/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ +/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ +/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ +#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ + /* explicitly cleared by SW) */ +/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ +/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ +/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ +/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ +#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ +#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ +/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ +#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ +#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ +/* FLCTL_ERASE_CTLSTAT[START] Bits */ +#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ +/* FLCTL_ERASE_CTLSTAT[MODE] Bits */ +#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ +/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ +#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ +#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ +#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ +#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ +#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ +#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ +#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ +/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ +#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ +#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ +#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ +#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ +#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ +#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ +#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ + /* unless explicitly cleared by SW) */ +/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ +#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ + /* address */ +/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ +#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ +#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ +/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ +#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ +#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ +/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ +#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ +#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ +/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ +#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ +#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ +/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ +/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ +#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ +#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ +/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ +#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ +#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ +/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ +#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ +/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ +#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ +#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) +/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ +#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ +#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) +/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ +#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ +#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) +/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ +#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ +#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) +/* FLCTL_IFG[RDBRST] Bits */ +#define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ +#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) +/* FLCTL_IFG[AVPRE] Bits */ +#define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ +#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) +/* FLCTL_IFG[AVPST] Bits */ +#define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ +#define FLCTL_IFG_AVPST ((uint32_t)0x00000004) +/* FLCTL_IFG[PRG] Bits */ +#define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ +#define FLCTL_IFG_PRG ((uint32_t)0x00000008) +/* FLCTL_IFG[PRGB] Bits */ +#define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ +#define FLCTL_IFG_PRGB ((uint32_t)0x00000010) +/* FLCTL_IFG[ERASE] Bits */ +#define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ +#define FLCTL_IFG_ERASE ((uint32_t)0x00000020) +/* FLCTL_IFG[BMRK] Bits */ +#define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ +#define FLCTL_IFG_BMRK ((uint32_t)0x00000100) +/* FLCTL_IFG[PRG_ERR] Bits */ +#define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ +#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) +/* FLCTL_IE[RDBRST] Bits */ +#define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ +#define FLCTL_IE_RDBRST ((uint32_t)0x00000001) +/* FLCTL_IE[AVPRE] Bits */ +#define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ +#define FLCTL_IE_AVPRE ((uint32_t)0x00000002) +/* FLCTL_IE[AVPST] Bits */ +#define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ +#define FLCTL_IE_AVPST ((uint32_t)0x00000004) +/* FLCTL_IE[PRG] Bits */ +#define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ +#define FLCTL_IE_PRG ((uint32_t)0x00000008) +/* FLCTL_IE[PRGB] Bits */ +#define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ +#define FLCTL_IE_PRGB ((uint32_t)0x00000010) +/* FLCTL_IE[ERASE] Bits */ +#define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ +#define FLCTL_IE_ERASE ((uint32_t)0x00000020) +/* FLCTL_IE[BMRK] Bits */ +#define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ +#define FLCTL_IE_BMRK ((uint32_t)0x00000100) +/* FLCTL_IE[PRG_ERR] Bits */ +#define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ +#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) +/* FLCTL_CLRIFG[RDBRST] Bits */ +#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ +#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) +/* FLCTL_CLRIFG[AVPRE] Bits */ +#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ +#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) +/* FLCTL_CLRIFG[AVPST] Bits */ +#define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ +#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) +/* FLCTL_CLRIFG[PRG] Bits */ +#define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ +#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) +/* FLCTL_CLRIFG[PRGB] Bits */ +#define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ +#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) +/* FLCTL_CLRIFG[ERASE] Bits */ +#define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ +#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) +/* FLCTL_CLRIFG[BMRK] Bits */ +#define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ +#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) +/* FLCTL_CLRIFG[PRG_ERR] Bits */ +#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ +#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) +/* FLCTL_SETIFG[RDBRST] Bits */ +#define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ +#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) +/* FLCTL_SETIFG[AVPRE] Bits */ +#define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ +#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) +/* FLCTL_SETIFG[AVPST] Bits */ +#define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ +#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) +/* FLCTL_SETIFG[PRG] Bits */ +#define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ +#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) +/* FLCTL_SETIFG[PRGB] Bits */ +#define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ +#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) +/* FLCTL_SETIFG[ERASE] Bits */ +#define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ +#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) +/* FLCTL_SETIFG[BMRK] Bits */ +#define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ +#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) +/* FLCTL_SETIFG[PRG_ERR] Bits */ +#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ +#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) +/* FLCTL_READ_TIMCTL[SETUP] Bits */ +#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ +#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ +#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ +/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ +#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ +#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ +/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ +#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ +#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ +#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ +#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ +/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ +#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ +#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ +/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ +#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ +#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ +#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ +#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ +#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ +/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ +#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ +#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ +/* FLCTL_ERASE_TIMCTL[SETUP] Bits */ +#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ +#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ +/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ +#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ +#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ +/* FLCTL_ERASE_TIMCTL[HOLD] Bits */ +#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ +#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ +/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ +#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ +#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ +/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ +#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ +#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ +/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ +#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ +#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ + +/****************************************************************************** +* FL_BOOTOVER_MAILBOX Bits +******************************************************************************/ + +/****************************************************************************** +* FPB Bits +******************************************************************************/ + + +/****************************************************************************** +* FPU Bits +******************************************************************************/ + + +/****************************************************************************** +* ITM Bits +******************************************************************************/ + + +/****************************************************************************** +* MPU Bits +******************************************************************************/ + +/* Pre-defined bitfield values */ + +/* MPU_RASR_SIZE Bitfield Bits */ +#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ +#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ +#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ +#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ +#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ +#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ +#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ +#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ +#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ +#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ +#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ +#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ +#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ +#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ +#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ +#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ +#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ +#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ +#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ +#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ +#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ +#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ +#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ +#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ +#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ +#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ +#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ +#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ + +/* MPU_RASR_AP Bitfield Bits */ +#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ +#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ +#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ +#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ +#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ +#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ + +/* MPU_RASR_XN Bitfield Bits */ +#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ +#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ + + +/****************************************************************************** +* NVIC Bits +******************************************************************************/ + +/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ +#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ +#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ +#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ +#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ +#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ +#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ +#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ +#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ +#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ +#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ +#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ +#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ +#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ +#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ +#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ +#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ +#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ +#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ +#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ +#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ +#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ +#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ +#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ +#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ +#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ +#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ +#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ +#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ +#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ +#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ +#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ +#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ +#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ +#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ +#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ +#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ +#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ +#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ +#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ +#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ +#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ +#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ +#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ +#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ +#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ +#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ +#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ +#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ +#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ +#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ +#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ +#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ +#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ +#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ +#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ +#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ +#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ +#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ +#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ +#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ +#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ +#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ +#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ +#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ +#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ +#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ +#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ +#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ +#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ +#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ +#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ +#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ +#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ +#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ +#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ +#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ +#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ +#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ +#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ +#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ +#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ +#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ +#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ +#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ +#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ +#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ +#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ +#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ +#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ +#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ +#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ +#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ +#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ +#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ +#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ +#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ +#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ +#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ +#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ +#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ +#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ +#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ +#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ +#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ +#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ +#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ +#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ +#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ +#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ +#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ +#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ +#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ +#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ +#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ +#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ +#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ +#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ +#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ +#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ +#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ +/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ +#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ +#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ +/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ +#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ +#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ +/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ +#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ +#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ +/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ +#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ +#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ + + +/****************************************************************************** +* PCM Bits +******************************************************************************/ +/* PCM_CTL0[AMR] Bits */ +#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ +#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ +#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ +#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ +#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ +#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ +#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ +/* PCM_CTL0[LPMR] Bits */ +#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ +#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ +#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ +#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ +#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ +#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ +#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ + /* entered. */ +#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ +#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ +#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ + /* entered. */ +#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ +#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ +/* PCM_CTL0[CPM] Bits */ +#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ +#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ +#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ +#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ +#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ +#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ +#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ +#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ +#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ +#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ +#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ +#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ +#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ +#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ +/* PCM_CTL0[KEY] Bits */ +#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ +#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ +/* PCM_CTL1[LOCKLPM5] Bits */ +#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ +#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ +/* PCM_CTL1[LOCKBKUP] Bits */ +#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ +#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ +/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ +#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ +#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ +/* PCM_CTL1[PMR_BUSY] Bits */ +#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ +#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ +/* PCM_CTL1[KEY] Bits */ +#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ +#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ +/* PCM_IE[LPM_INVALID_TR_IE] Bits */ +#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ +#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ +/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ +#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ +#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ +/* PCM_IE[AM_INVALID_TR_IE] Bits */ +#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ +#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ +/* PCM_IE[DCDC_ERROR_IE] Bits */ +#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ +#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ +/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ +#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ +#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ +/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ +#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ +#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ +/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ +#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ +#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ +/* PCM_IFG[DCDC_ERROR_IFG] Bits */ +#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ +#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ +/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ +#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ +#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ +/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ +#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ +#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ +/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ +#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ +#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ +/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ +#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ +#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ +/* Pre-defined bitfield values */ +#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ +#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ + + +/****************************************************************************** +* PMAP Bits +******************************************************************************/ +/* PMAP_CTL[LOCKED] Bits */ +#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ +#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ +/* PMAP_CTL[PRECFG] Bits */ +#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ +#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ +/* Pre-defined bitfield values */ +#define PMAP_NONE 0 +#define PMAP_UCA0CLK 1 +#define PMAP_UCA0RXD 2 +#define PMAP_UCA0SOMI 2 +#define PMAP_UCA0TXD 3 +#define PMAP_UCA0SIMO 3 +#define PMAP_UCB0CLK 4 +#define PMAP_UCB0SDA 5 +#define PMAP_UCB0SIMO 5 +#define PMAP_UCB0SCL 6 +#define PMAP_UCB0SOMI 6 +#define PMAP_UCA1STE 7 +#define PMAP_UCA1CLK 8 +#define PMAP_UCA1RXD 9 +#define PMAP_UCA1SOMI 9 +#define PMAP_UCA1TXD 10 +#define PMAP_UCA1SIMO 10 +#define PMAP_UCA2STE 11 +#define PMAP_UCA2CLK 12 +#define PMAP_UCA2RXD 13 +#define PMAP_UCA2SOMI 13 +#define PMAP_UCA2TXD 14 +#define PMAP_UCA2SIMO 14 +#define PMAP_UCB2STE 15 +#define PMAP_UCB2CLK 16 +#define PMAP_UCB2SDA 17 +#define PMAP_UCB2SIMO 17 +#define PMAP_UCB2SCL 18 +#define PMAP_UCB2SOMI 18 +#define PMAP_TA0CCR0A 19 +#define PMAP_TA0CCR1A 20 +#define PMAP_TA0CCR2A 21 +#define PMAP_TA0CCR3A 22 +#define PMAP_TA0CCR4A 23 +#define PMAP_TA1CCR1A 24 +#define PMAP_TA1CCR2A 25 +#define PMAP_TA1CCR3A 26 +#define PMAP_TA1CCR4A 27 +#define PMAP_TA0CLK 28 +#define PMAP_CE0OUT 28 +#define PMAP_TA1CLK 29 +#define PMAP_CE1OUT 29 +#define PMAP_DMAE0 30 +#define PMAP_SMCLK 30 +#define PMAP_ANALOG 31 + +#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ + + +/****************************************************************************** +* PSS Bits +******************************************************************************/ +/* PSS_KEY[KEY] Bits */ +#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ +#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ +/* PSS_CTL0[SVSMHOFF] Bits */ +#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ +#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ +/* PSS_CTL0[SVSMHLP] Bits */ +#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ +#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ +/* PSS_CTL0[SVSMHS] Bits */ +#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ +#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ +/* PSS_CTL0[SVSMHTH] Bits */ +#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ +#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ +/* PSS_CTL0[SVMHOE] Bits */ +#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ +#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ +/* PSS_CTL0[SVMHOUTPOLAL] Bits */ +#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ +#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ +/* PSS_CTL0[DCDC_FORCE] Bits */ +#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ +#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ +/* PSS_CTL0[VCORETRAN] Bits */ +#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ +#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ +#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ +#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ +#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ +#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ +#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ +#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ +#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ +#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ +#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ +#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ +/* PSS_IE[SVSMHIE] Bits */ +#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ +#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ +/* PSS_IFG[SVSMHIFG] Bits */ +#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ +#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ +/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ +#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ +#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ +/* Pre-defined bitfield values */ +#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ + + +/****************************************************************************** +* REF_A Bits +******************************************************************************/ +/* REF_A_CTL0[ON] Bits */ +#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ +#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ +/* REF_A_CTL0[OUT] Bits */ +#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ +#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ +/* REF_A_CTL0[TCOFF] Bits */ +#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ +#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ +/* REF_A_CTL0[VSEL] Bits */ +#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ +#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ +#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ +#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ +#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ +#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ +#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ +/* REF_A_CTL0[GENOT] Bits */ +#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ +#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ +/* REF_A_CTL0[BGOT] Bits */ +#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ +#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ +/* REF_A_CTL0[GENACT] Bits */ +#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ +#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ +/* REF_A_CTL0[BGACT] Bits */ +#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ +#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ +/* REF_A_CTL0[GENBUSY] Bits */ +#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ +#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ +/* REF_A_CTL0[BGMODE] Bits */ +#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ +#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ +/* REF_A_CTL0[GENRDY] Bits */ +#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ +#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ +/* REF_A_CTL0[BGRDY] Bits */ +#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ +#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ + +/****************************************************************************** +* RSTCTL Bits +******************************************************************************/ +/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ +#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ +#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ +/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ +#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ +#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ +/* RSTCTL_RESET_REQ[RSTKEY] Bits */ +#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ +#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ +/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ +#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ +/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ +/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ +#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ +/* RSTCTL_HARDRESET_SET[SRC0] Bits */ +#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC1] Bits */ +#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC2] Bits */ +#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC3] Bits */ +#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC4] Bits */ +#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC5] Bits */ +#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC6] Bits */ +#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC7] Bits */ +#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC8] Bits */ +#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC9] Bits */ +#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC10] Bits */ +#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC11] Bits */ +#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC12] Bits */ +#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC13] Bits */ +#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC14] Bits */ +#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_HARDRESET_SET[SRC15] Bits */ +#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ + /* initiates a Hard Reset) */ +/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ +#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ +/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ +#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ +/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ +#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ +#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ + /* initiates a Soft Reset) */ +/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ +#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ +#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ +/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ +#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ +#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ +/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ +#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ +#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ +/* RSTCTL_PSSRESET_CLR[CLR] Bits */ +#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ +#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ +/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ +#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ +#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ +/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ +#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ +#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ +/* RSTCTL_PCMRESET_CLR[CLR] Bits */ +#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ +#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ +/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ +#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ +#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ +/* RSTCTL_PINRESET_CLR[CLR] Bits */ +#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ +#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ +/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ +#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ +#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ +/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ +#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ +#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ +/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ +#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ +#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ + /* resistor mode */ +/* RSTCTL_CSRESET_CLR[CLR] Bits */ +#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ +#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ + /* DCOR_SHTIFG flag in CSIFG register of clock system */ +/* Pre-defined bitfield values */ +#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ + + +/****************************************************************************** +* RTC_C Bits +******************************************************************************/ +/* RTC_C_CTL0[RDYIFG] Bits */ +#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ +#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ +/* RTC_C_CTL0[AIFG] Bits */ +#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ +#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ +/* RTC_C_CTL0[TEVIFG] Bits */ +#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ +#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ +/* RTC_C_CTL0[OFIFG] Bits */ +#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ +#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ +/* RTC_C_CTL0[RDYIE] Bits */ +#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ +#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ +/* RTC_C_CTL0[AIE] Bits */ +#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ +#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ +/* RTC_C_CTL0[TEVIE] Bits */ +#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ +#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ +/* RTC_C_CTL0[OFIE] Bits */ +#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ +#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ +/* RTC_C_CTL0[KEY] Bits */ +#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ +#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ +/* RTC_C_CTL13[TEV] Bits */ +#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ +#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ +#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ +#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ +#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ +#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ +#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ +#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ +/* RTC_C_CTL13[SSEL] Bits */ +#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ +#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ +#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ +#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ +#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ +#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ +/* RTC_C_CTL13[RDY] Bits */ +#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ +#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ +/* RTC_C_CTL13[MODE] Bits */ +#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ +#define RTC_C_CTL13_MODE ((uint16_t)0x0020) +/* RTC_C_CTL13[HOLD] Bits */ +#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ +#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ +/* RTC_C_CTL13[BCD] Bits */ +#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ +#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ +/* RTC_C_CTL13[CALF] Bits */ +#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ +#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ +#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ +#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ +#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ +#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ +#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ +#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ +#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ +#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ +#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ +#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ +/* RTC_C_OCAL[OCAL] Bits */ +#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ +#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ +/* RTC_C_OCAL[OCALS] Bits */ +#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ +#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ +/* RTC_C_TCMP[TCMPx] Bits */ +#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ +#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ +/* RTC_C_TCMP[TCOK] Bits */ +#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ +#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ +/* RTC_C_TCMP[TCRDY] Bits */ +#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ +#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ +/* RTC_C_TCMP[TCMPS] Bits */ +#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ +#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ +/* RTC_C_PS0CTL[RT0PSIFG] Bits */ +#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ +#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ +/* RTC_C_PS0CTL[RT0PSIE] Bits */ +#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ +#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ +/* RTC_C_PS0CTL[RT0IP] Bits */ +#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ +#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ +#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ +#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ +#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ +#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ +#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ +#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ +#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ +#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ +#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ +#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ +#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ +#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ +#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ +#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ +#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ +#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ +#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ +#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ +#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ +/* RTC_C_PS1CTL[RT1PSIFG] Bits */ +#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ +#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ +/* RTC_C_PS1CTL[RT1PSIE] Bits */ +#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ +#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ +/* RTC_C_PS1CTL[RT1IP] Bits */ +#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ +#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ +#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ +#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ +#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ +#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ +#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ +#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ +#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ +#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ +#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ +#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ +#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ +#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ +#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ +#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ +#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ +#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ +#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ +#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ +#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ +/* RTC_C_PS[RT0PS] Bits */ +#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ +#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ +/* RTC_C_PS[RT1PS] Bits */ +#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ +#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ +/* RTC_C_TIM0[SEC] Bits */ +#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ +#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ +/* RTC_C_TIM0[MIN] Bits */ +#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ +#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ +/* RTC_C_TIM0[SEC_LD] Bits */ +#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ +#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ +/* RTC_C_TIM0[SEC_HD] Bits */ +#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ +#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ +/* RTC_C_TIM0[MIN_LD] Bits */ +#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ +#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ +/* RTC_C_TIM0[MIN_HD] Bits */ +#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ +#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ +/* RTC_C_TIM1[HOUR] Bits */ +#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ +#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ +/* RTC_C_TIM1[DOW] Bits */ +#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ +#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ +/* RTC_C_TIM1[HOUR_LD] Bits */ +#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ +#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ +/* RTC_C_TIM1[HOUR_HD] Bits */ +#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ +#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ +/* RTC_C_DATE[DAY] Bits */ +#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ +#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ +/* RTC_C_DATE[MON] Bits */ +#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ +#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ +/* RTC_C_DATE[DAY_LD] Bits */ +#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ +#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ +/* RTC_C_DATE[DAY_HD] Bits */ +#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ +#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ +/* RTC_C_DATE[MON_LD] Bits */ +#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ +#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ +/* RTC_C_DATE[MON_HD] Bits */ +#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ +#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ +/* RTC_C_YEAR[YEAR_LB] Bits */ +#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ +#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ +/* RTC_C_YEAR[YEAR_HB] Bits */ +#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ +#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ +/* RTC_C_YEAR[YEAR] Bits */ +#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ +#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ +/* RTC_C_YEAR[DEC] Bits */ +#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ +#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ +/* RTC_C_YEAR[CENT_LD] Bits */ +#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ +#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ +/* RTC_C_YEAR[CENT_HD] Bits */ +#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ +#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ +/* RTC_C_AMINHR[MIN] Bits */ +#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ +#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ +/* RTC_C_AMINHR[MINAE] Bits */ +#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ +#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ +/* RTC_C_AMINHR[HOUR] Bits */ +#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ +#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ +/* RTC_C_AMINHR[HOURAE] Bits */ +#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ +#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ +/* RTC_C_AMINHR[MIN_LD] Bits */ +#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ +#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ +/* RTC_C_AMINHR[MIN_HD] Bits */ +#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ +#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ +/* RTC_C_AMINHR[HOUR_LD] Bits */ +#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ +#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ +/* RTC_C_AMINHR[HOUR_HD] Bits */ +#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ +#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ +/* RTC_C_ADOWDAY[DOW] Bits */ +#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ +#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ +/* RTC_C_ADOWDAY[DOWAE] Bits */ +#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ +#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ +/* RTC_C_ADOWDAY[DAY] Bits */ +#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ +#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ +/* RTC_C_ADOWDAY[DAYAE] Bits */ +#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ +#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ +/* RTC_C_ADOWDAY[DAY_LD] Bits */ +#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ +#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ +/* RTC_C_ADOWDAY[DAY_HD] Bits */ +#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ +#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ +/* Pre-defined bitfield values */ +#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ +#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ +#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ + + +/****************************************************************************** +* SCB Bits +******************************************************************************/ +/* SCB_PFR0[STATE0] Bits */ +#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ +#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ +#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ +#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ +#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ +#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ +#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ +#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ +/* SCB_PFR0[STATE1] Bits */ +#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ +#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ +#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ +#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ +#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ +#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ +#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ +#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ +#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ + /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ + /* can be added using the appropriate instruction attribute, but other 32-bit */ + /* basic instructions cannot.) */ +#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ +/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ +#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ +/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ +#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ +/* SCB_MMFR0[PMSA_SUPPORT] Bits */ +#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ +#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ +#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ +#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ +#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ +#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ +#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ +#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ +#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ +#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ +/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ + /* the entities within an inner-coherent domain) */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ + /* inner-coherent domain) */ +#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ +/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ +#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ +/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ +#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ +/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ +#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ +/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ +#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ +#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ +#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ +#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ +#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ +#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ +#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ +#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ +/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ +#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ +#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ +#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ +#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ +#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ +#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ +#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ +#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ +/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ +#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ +#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ +#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ +#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ +#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ +#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ +#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ +#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ +/* SCB_ISAR0[COPROC_INSTRS] Bits */ +#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ +#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ +#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ +#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ +#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ +#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ +#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ + /* such as CP15 or VFP */ +#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ +#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ +#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ +#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ +/* SCB_ISAR0[DEBUG_INSTRS] Bits */ +#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ +#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ +#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ +#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ +#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ +#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ +#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ +#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ +/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ +#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ +#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ +#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ +#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ +#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ +#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ +#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ +#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ +/* SCB_ISAR1[ETEND_INSRS] Bits */ +#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ +#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ +#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ +#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ +#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ +#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ +#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ +#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ +#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ +/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ +#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ +#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ +#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ +#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ +#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ +#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ +#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ +#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ +/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ +#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ +#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ +#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ +#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ +#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ +#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ +#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ +#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ +/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ +#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ +#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ +#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ +#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ +#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ +#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ +#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ +#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ +#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ +#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ +/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ +#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ +#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ +#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ +#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ +#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ +#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ +#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ +#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ +/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ +#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ +#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ +#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ +#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ +#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ +#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ +#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ +#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ +#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ +#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ +/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ +#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ +/* SCB_ISAR2[MULT_INSTRS] Bits */ +#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ +#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ +#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ +#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ +#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ +#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ +#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ +#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ +#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ +/* SCB_ISAR2[MULTS_INSTRS] Bits */ +#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ +#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ +#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ +#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ +#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ +#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ +#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ +#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ +#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ +#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ +/* SCB_ISAR2[MULTU_INSTRS] Bits */ +#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ +#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ +#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ +#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ +#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ +#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ +#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ +#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ +#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ +/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ +#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ +#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ +#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ +#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ +#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ +#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ +#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ +#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ +#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ +/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ +#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ +#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ +#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ +#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ +#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ +#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ +#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ +#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ +/* SCB_ISAR3[SIMD_INSTRS] Bits */ +#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ +#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ +#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ +#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ +#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ +#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ +#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ +#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ +#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ +/* SCB_ISAR3[SVC_INSTRS] Bits */ +#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ +#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ +#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ +#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ +#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ +#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ +#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ +#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ +/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ +#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ +#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ +#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ +#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ +#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ +#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ +#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ +#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ +#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ +/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ +#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ +#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ +#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ +#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ +#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ +#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ +#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ +#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ +/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ +#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ +#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ +#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ +#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ +#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ +#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ +#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ +#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ +/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ +#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ +#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ +#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ +#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ +#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ +#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ +#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ + /* register dependencies */ +#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ +/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ +#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ +#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ +#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ +#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ +#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ +#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ +#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ +#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ +#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ +/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ +#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ +/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ +#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ +#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ +#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ +#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ +#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ +#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ +#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ + /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ +#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ +/* SCB_ISAR4[BARRIER_INSTRS] Bits */ +#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ +#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ +#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ +#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ +#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ +#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ +#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ +#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ +/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ +#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ +/* SCB_ISAR4[PSR_M_INSTRS] Bits */ +#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ +#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ +#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ +#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ +#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ +#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ +#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ +#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ +/* SCB_CPACR[CP11] Bits */ +#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ +#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ +/* SCB_CPACR[CP10] Bits */ +#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ +#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ +/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ +#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ +#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ +/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ +#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ +#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ +/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ +#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ +#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ +/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ +#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ +#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ +/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ +#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ +#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ +/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ +#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ +#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ +/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ +#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ +#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ +/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ +#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ +#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ +/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ +#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ +#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ +/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ +#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ +#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ +/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ +#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ +#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ +/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ +#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ +#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ + +/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ +#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ +/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ +#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ +/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ +#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ +/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ +#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ +/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ +#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ +/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ +#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ +/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ +#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ +/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ +#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ +/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ +#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ +/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ +#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ +/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ +#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ +/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ +#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ +/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ +#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ +/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ +#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ +/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ +#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ +/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ +#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ +/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ +#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ +/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ +#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ +#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ +/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ +#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ +#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ + + +/****************************************************************************** +* SCNSCB Bits +******************************************************************************/ + + +/****************************************************************************** +* SYSCTL Bits +******************************************************************************/ +/* SYSCTL_REBOOT_CTL[REBOOT] Bits */ +#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ +#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ +/* SYSCTL_REBOOT_CTL[WKEY] Bits */ +#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ +#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ +/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ +#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ +#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ +#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ +#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) +/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ +#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ +#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ +#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ +/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ +#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ +#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ +/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ +#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ +#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ +/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ +#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ +#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ +/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ +#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ +#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ +/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ +/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ +#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ +#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ +/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ +#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ +#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ +/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ +/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ +/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ +/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ +/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ +/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ +/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ +/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ +#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ +#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ +/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ +#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ +#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ +/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ +#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ +#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ +/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ +#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ +#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ +/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ +#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ +#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ +/* SYSCTL_RESET_REQ[POR] Bits */ +#define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ +#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ +/* SYSCTL_RESET_REQ[REBOOT] Bits */ +#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ +#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ +/* SYSCTL_RESET_REQ[WKEY] Bits */ +#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ +#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ +/* SYSCTL_RESET_STATOVER[SOFT] Bits */ +#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ +#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ +/* SYSCTL_RESET_STATOVER[HARD] Bits */ +#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ +#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ +/* SYSCTL_RESET_STATOVER[REBOOT] Bits */ +#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ +#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ +/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ +#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ +#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ +/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ +#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ +#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ +/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ +#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ +#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ +/* Pre-defined bitfield values */ +#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ + /* cleared */ + + +/****************************************************************************** +* SYSTICK Bits +******************************************************************************/ + +/****************************************************************************** +* Timer32 Bits +******************************************************************************/ +/* TIMER32_CONTROL[ONESHOT] Bits */ +#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ +#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ +/* TIMER32_CONTROL[SIZE] Bits */ +#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ +#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ +/* TIMER32_CONTROL[PRESCALE] Bits */ +#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ +#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ +#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ +#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ +#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ +#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ +#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ +/* TIMER32_CONTROL[IE] Bits */ +#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ +#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ +/* TIMER32_CONTROL[MODE] Bits */ +#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ +#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ +/* TIMER32_CONTROL[ENABLE] Bits */ +#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ +#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) +/* TIMER32_RIS[RAW_IFG] Bits */ +#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ +#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ +/* TIMER32_MIS[IFG] Bits */ +#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ +#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ + + + +/****************************************************************************** +* TIMER_A Bits +******************************************************************************/ +/* TIMER_A_CTL[IFG] Bits */ +#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ +#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ +/* TIMER_A_CTL[IE] Bits */ +#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ +#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ +/* TIMER_A_CTL[CLR] Bits */ +#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ +#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ +/* TIMER_A_CTL[MC] Bits */ +#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ +#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ +#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ +#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ +#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ +#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ +#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ +#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ +#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ +#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ +#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +/* TIMER_A_CTL[ID] Bits */ +#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ +#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ +#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ +#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ +#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ +#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ +#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ +#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ +#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ +#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ +#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ +#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ +/* TIMER_A_CTL[SSEL] Bits */ +#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ +#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ +#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ +#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ +#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ +#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ +#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ +#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ +#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ +#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ +#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ +#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ +/* TIMER_A_CCTLN[CCIFG] Bits */ +#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ +#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ +/* TIMER_A_CCTLN[COV] Bits */ +#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ +#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ +/* TIMER_A_CCTLN[OUT] Bits */ +#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ +#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ +/* TIMER_A_CCTLN[CCI] Bits */ +#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ +#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ +/* TIMER_A_CCTLN[CCIE] Bits */ +#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ +#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ +/* TIMER_A_CCTLN[OUTMOD] Bits */ +#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ +#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ +#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ +#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ +#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ +#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ +#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ +#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ +#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ +#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ +#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ +#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ +#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ +/* TIMER_A_CCTLN[CAP] Bits */ +#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ +#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ +/* TIMER_A_CCTLN[SCCI] Bits */ +#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ +#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ +/* TIMER_A_CCTLN[SCS] Bits */ +#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ +#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ +/* TIMER_A_CCTLN[CCIS] Bits */ +#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ +#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ +#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ +#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ +#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ +#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ +#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ +#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ +#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ +#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ +#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ +#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ +/* TIMER_A_CCTLN[CM] Bits */ +#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ +#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ +#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ +#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ +#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ +#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ +#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ +#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ +#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ +#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ +#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ +#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ +/* TIMER_A_EX0[IDEX] Bits */ +#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ +#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ +#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ +#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ +#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ +#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ +#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ +#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ +#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ +#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ +#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ +#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ +#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ +#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ +#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ +#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ +#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ +#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ +#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ +#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ +#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ + +/****************************************************************************** +* TLV Bits +******************************************************************************/ +/****************************************************************************** +* TLV table start and TLV tags * +******************************************************************************/ +#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ + +#define TLV_TAG_RESERVED1 1 +#define TLV_TAG_RESERVED2 2 +#define TLV_TAG_CS 3 +#define TLV_TAG_FLASHCTL 4 +#define TLV_TAG_ADC14 5 +#define TLV_TAG_RESERVED6 6 +#define TLV_TAG_RESERVED7 7 +#define TLV_TAG_REF 8 +#define TLV_TAG_RESERVED9 9 +#define TLV_TAG_RESERVED10 10 +#define TLV_TAG_DEVINFO 11 +#define TLV_TAG_DIEREC 12 +#define TLV_TAG_RANDNUM 13 +#define TLV_TAG_RESERVED14 14 +#define TLV_TAG_BSL 15 +#define TLV_TAG_END (0x0BD0E11D) + + +/****************************************************************************** +* TPIU Bits +******************************************************************************/ + + +/****************************************************************************** +* WDT_A Bits +******************************************************************************/ +/* WDT_A_CTL[IS] Bits */ +#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ +#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ +#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ +#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ +#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ +#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ +#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ +#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ +#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ +#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ +#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ +#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ +#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ +/* WDT_A_CTL[CNTCL] Bits */ +#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ +#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ +/* WDT_A_CTL[TMSEL] Bits */ +#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ +#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ +/* WDT_A_CTL[SSEL] Bits */ +#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ +#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ +#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ +#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ +#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ +#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ +#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ +#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ +#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ +#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ +#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ +#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ +/* WDT_A_CTL[HOLD] Bits */ +#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ +#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ +/* WDT_A_CTL[PW] Bits */ +#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ +#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ +/* Pre-defined bitfield values */ +#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ + + +/****************************************************************************** +* BSL * +******************************************************************************/ +#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ +#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ +#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) + +#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ +#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ +#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ +#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ + +#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ + + +/****************************************************************************** +* Mailbox struct legacy definition * +******************************************************************************/ +#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type + +/****************************************************************************** +* Device Unlock Support * +******************************************************************************/ +/* unlock the device by: + * Load SYSCTL_SECDATA_UNLOCK register address into R0 + * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 + * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register + */ +#define UNLOCK_DEVICE\ + __asm(" MOVW.W R0, #0x3040");\ + __asm(" MOVT.W R0, #0xE004");\ + __asm(" MOVW.W R1, #0x695A");\ + __asm(" MOVT.W R1, #0x0000");\ + __asm(" STR R1, [R0]"); + +/****************************************************************************** +* +* The following are values that can be used to choose the command that will be +* run by the boot code. Perform a logical OR of these settings to create your +* general parameter command. +* +******************************************************************************/ +#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) +#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) +#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) +#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) +#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) +#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) +#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) +#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) +#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) +#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) +#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) +#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) +#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) + +/****************************************************************************** +* +* The following are values that can be used to configure the BSL. Perform a +* logical OR of these settings to create your BSL parameter. +* +******************************************************************************/ +#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) + +#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) +#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) +#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) + +#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) +#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) +#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) +#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) +#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) +#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) +#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) +#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) + +#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) +#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) + +#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) +#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) +#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) +#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) + +#define BSL_CONFIG_I2C_ADD_OFFSET (16) + + +/****************************************************************************** +* ULP Advisor * +******************************************************************************/ +#ifdef __TI_ARM__ +#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) +#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) +#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) +#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) +#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) +#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) +#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) +#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) +#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) +#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __MSP432P401R_H__ */ + diff --git a/inc/msp432p401r_classic.h b/inc/msp432p401r_classic.h new file mode 100644 index 0000000..21e2bda --- /dev/null +++ b/inc/msp432p401r_classic.h @@ -0,0 +1,3623 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* MSP432P401R Register Definitions +* +* This file includes MSP430 style component and register definitions +* for legacy components re-used in MSP432 +* +* File creation date: 2018-01-26 +* +******************************************************************************/ + +#ifndef __MSP432P401R_CLASSIC_H__ +#define __MSP432P401R_CLASSIC_H__ + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/****************************************************************************** +* Device memory map * +******************************************************************************/ +#define __MAIN_MEMORY_START__ (0x00000000) /*!< Main Flash memory start address */ +#define __MAIN_MEMORY_END__ (0x0003FFFF) /*!< Main Flash memory end address */ +#define __BSL_MEMORY_START__ (0x00202000) /*!< BSL memory start address */ +#define __BSL_MEMORY_END__ (0x00203FFF) /*!< BSL memory end address */ +#define __SRAM_START__ (0x20000000) /*!< SRAM memory start address */ +#define __SRAM_END__ (0x2000FFFF) /*!< SRAM memory end address */ + +/****************************************************************************** +* MSP-format peripheral registers * +******************************************************************************/ + +/****************************************************************************** +* AES256 Registers +******************************************************************************/ +#define AESACTL0 (HWREG16(0x40003C00)) /*!< AES Accelerator Control Register 0 */ +#define AESACTL1 (HWREG16(0x40003C02)) /*!< AES Accelerator Control Register 1 */ +#define AESASTAT (HWREG16(0x40003C04)) /*!< AES Accelerator Status Register */ +#define AESAKEY (HWREG16(0x40003C06)) /*!< AES Accelerator Key Register */ +#define AESADIN (HWREG16(0x40003C08)) /*!< AES Accelerator Data In Register */ +#define AESADOUT (HWREG16(0x40003C0A)) /*!< AES Accelerator Data Out Register */ +#define AESAXDIN (HWREG16(0x40003C0C)) /*!< AES Accelerator XORed Data In Register */ +#define AESAXIN (HWREG16(0x40003C0E)) /*!< AES Accelerator XORed Data In Register */ + +/* Register offsets from AES256_BASE address */ +#define OFS_AESACTL0 (0x0000) /*!< AES Accelerator Control Register 0 */ +#define OFS_AESACTL1 (0x0002) /*!< AES Accelerator Control Register 1 */ +#define OFS_AESASTAT (0x0004) /*!< AES Accelerator Status Register */ +#define OFS_AESAKEY (0x0006) /*!< AES Accelerator Key Register */ +#define OFS_AESADIN (0x0008) /*!< AES Accelerator Data In Register */ +#define OFS_AESADOUT (0x000A) /*!< AES Accelerator Data Out Register */ +#define OFS_AESAXDIN (0x000C) /*!< AES Accelerator XORed Data In Register */ +#define OFS_AESAXIN (0x000E) /*!< AES Accelerator XORed Data In Register */ + + +/****************************************************************************** +* CAPTIO0 Registers +******************************************************************************/ +#define CAPTIO0CTL (HWREG16(0x4000540E)) /*!< Capacitive Touch IO x Control Register */ + +/* Register offsets from CAPTIO0_BASE address */ +#define OFS_CAPTIO0CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ + +#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ +#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ + +/****************************************************************************** +* CAPTIO1 Registers +******************************************************************************/ +#define CAPTIO1CTL (HWREG16(0x4000580E)) /*!< Capacitive Touch IO x Control Register */ + +/* Register offsets from CAPTIO1_BASE address */ +#define OFS_CAPTIO1CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ + +#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ +#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ + +/****************************************************************************** +* COMP_E0 Registers +******************************************************************************/ +#define CE0CTL0 (HWREG16(0x40003400)) /*!< Comparator Control Register 0 */ +#define CE0CTL1 (HWREG16(0x40003402)) /*!< Comparator Control Register 1 */ +#define CE0CTL2 (HWREG16(0x40003404)) /*!< Comparator Control Register 2 */ +#define CE0CTL3 (HWREG16(0x40003406)) /*!< Comparator Control Register 3 */ +#define CE0INT (HWREG16(0x4000340C)) /*!< Comparator Interrupt Control Register */ +#define CE0IV (HWREG16(0x4000340E)) /*!< Comparator Interrupt Vector Word Register */ + +/* Register offsets from COMP_E0_BASE address */ +#define OFS_CE0CTL0 (0x0000) /*!< Comparator Control Register 0 */ +#define OFS_CE0CTL1 (0x0002) /*!< Comparator Control Register 1 */ +#define OFS_CE0CTL2 (0x0004) /*!< Comparator Control Register 2 */ +#define OFS_CE0CTL3 (0x0006) /*!< Comparator Control Register 3 */ +#define OFS_CE0INT (0x000C) /*!< Comparator Interrupt Control Register */ +#define OFS_CE0IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ + + +/****************************************************************************** +* COMP_E1 Registers +******************************************************************************/ +#define CE1CTL0 (HWREG16(0x40003800)) /*!< Comparator Control Register 0 */ +#define CE1CTL1 (HWREG16(0x40003802)) /*!< Comparator Control Register 1 */ +#define CE1CTL2 (HWREG16(0x40003804)) /*!< Comparator Control Register 2 */ +#define CE1CTL3 (HWREG16(0x40003806)) /*!< Comparator Control Register 3 */ +#define CE1INT (HWREG16(0x4000380C)) /*!< Comparator Interrupt Control Register */ +#define CE1IV (HWREG16(0x4000380E)) /*!< Comparator Interrupt Vector Word Register */ + +/* Register offsets from COMP_E1_BASE address */ +#define OFS_CE1CTL0 (0x0000) /*!< Comparator Control Register 0 */ +#define OFS_CE1CTL1 (0x0002) /*!< Comparator Control Register 1 */ +#define OFS_CE1CTL2 (0x0004) /*!< Comparator Control Register 2 */ +#define OFS_CE1CTL3 (0x0006) /*!< Comparator Control Register 3 */ +#define OFS_CE1INT (0x000C) /*!< Comparator Interrupt Control Register */ +#define OFS_CE1IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ + + +/****************************************************************************** +* CRC32 Registers +******************************************************************************/ +#define CRC32DI (HWREG16(0x40004000)) /*!< Data Input for CRC32 Signature Computation */ +#define CRC32DIRB (HWREG16(0x40004004)) /*!< Data In Reverse for CRC32 Computation */ +#define CRC32INIRES_LO (HWREG16(0x40004008)) /*!< CRC32 Initialization and Result, lower 16 bits */ +#define CRC32INIRES_HI (HWREG16(0x4000400A)) /*!< CRC32 Initialization and Result, upper 16 bits */ +#define CRC32RESR_LO (HWREG16(0x4000400C)) /*!< CRC32 Result Reverse, lower 16 bits */ +#define CRC32RESR_HI (HWREG16(0x4000400E)) /*!< CRC32 Result Reverse, Upper 16 bits */ +#define CRC16DI (HWREG16(0x40004010)) /*!< Data Input for CRC16 computation */ +#define CRC16DIRB (HWREG16(0x40004014)) /*!< CRC16 Data In Reverse */ +#define CRC16INIRES (HWREG16(0x40004018)) /*!< CRC16 Initialization and Result register */ +#define CRC16RESR (HWREG16(0x4000401E)) /*!< CRC16 Result Reverse */ + +/* Register offsets from CRC32_BASE address */ +#define OFS_CRC32DI (0x0000) /*!< Data Input for CRC32 Signature Computation */ +#define OFS_CRC32DIRB (0x0004) /*!< Data In Reverse for CRC32 Computation */ +#define OFS_CRC32INIRES_LO (0x0008) /*!< CRC32 Initialization and Result, lower 16 bits */ +#define OFS_CRC32INIRES_HI (0x000A) /*!< CRC32 Initialization and Result, upper 16 bits */ +#define OFS_CRC32RESR_LO (0x000C) /*!< CRC32 Result Reverse, lower 16 bits */ +#define OFS_CRC32RESR_HI (0x000E) /*!< CRC32 Result Reverse, Upper 16 bits */ +#define OFS_CRC16DI (0x0010) /*!< Data Input for CRC16 computation */ +#define OFS_CRC16DIRB (0x0014) /*!< CRC16 Data In Reverse */ +#define OFS_CRC16INIRES (0x0018) /*!< CRC16 Initialization and Result register */ +#define OFS_CRC16RESR (0x001E) /*!< CRC16 Result Reverse */ + + +/****************************************************************************** +* DIO Registers +******************************************************************************/ +#define PAIN (HWREG16(0x40004C00)) /*!< Port A Input */ +#define PAOUT (HWREG16(0x40004C02)) /*!< Port A Output */ +#define PADIR (HWREG16(0x40004C04)) /*!< Port A Direction */ +#define PAREN (HWREG16(0x40004C06)) /*!< Port A Resistor Enable */ +#define PADS (HWREG16(0x40004C08)) /*!< Port A Drive Strength */ +#define PASEL0 (HWREG16(0x40004C0A)) /*!< Port A Select 0 */ +#define PASEL1 (HWREG16(0x40004C0C)) /*!< Port A Select 1 */ +#define P1IV (HWREG16(0x40004C0E)) /*!< Port 1 Interrupt Vector Register */ +#define PASELC (HWREG16(0x40004C16)) /*!< Port A Complement Select */ +#define PAIES (HWREG16(0x40004C18)) /*!< Port A Interrupt Edge Select */ +#define PAIE (HWREG16(0x40004C1A)) /*!< Port A Interrupt Enable */ +#define PAIFG (HWREG16(0x40004C1C)) /*!< Port A Interrupt Flag */ +#define P2IV (HWREG16(0x40004C1E)) /*!< Port 2 Interrupt Vector Register */ +#define PBIN (HWREG16(0x40004C20)) /*!< Port B Input */ +#define PBOUT (HWREG16(0x40004C22)) /*!< Port B Output */ +#define PBDIR (HWREG16(0x40004C24)) /*!< Port B Direction */ +#define PBREN (HWREG16(0x40004C26)) /*!< Port B Resistor Enable */ +#define PBDS (HWREG16(0x40004C28)) /*!< Port B Drive Strength */ +#define PBSEL0 (HWREG16(0x40004C2A)) /*!< Port B Select 0 */ +#define PBSEL1 (HWREG16(0x40004C2C)) /*!< Port B Select 1 */ +#define P3IV (HWREG16(0x40004C2E)) /*!< Port 3 Interrupt Vector Register */ +#define PBSELC (HWREG16(0x40004C36)) /*!< Port B Complement Select */ +#define PBIES (HWREG16(0x40004C38)) /*!< Port B Interrupt Edge Select */ +#define PBIE (HWREG16(0x40004C3A)) /*!< Port B Interrupt Enable */ +#define PBIFG (HWREG16(0x40004C3C)) /*!< Port B Interrupt Flag */ +#define P4IV (HWREG16(0x40004C3E)) /*!< Port 4 Interrupt Vector Register */ +#define PCIN (HWREG16(0x40004C40)) /*!< Port C Input */ +#define PCOUT (HWREG16(0x40004C42)) /*!< Port C Output */ +#define PCDIR (HWREG16(0x40004C44)) /*!< Port C Direction */ +#define PCREN (HWREG16(0x40004C46)) /*!< Port C Resistor Enable */ +#define PCDS (HWREG16(0x40004C48)) /*!< Port C Drive Strength */ +#define PCSEL0 (HWREG16(0x40004C4A)) /*!< Port C Select 0 */ +#define PCSEL1 (HWREG16(0x40004C4C)) /*!< Port C Select 1 */ +#define P5IV (HWREG16(0x40004C4E)) /*!< Port 5 Interrupt Vector Register */ +#define PCSELC (HWREG16(0x40004C56)) /*!< Port C Complement Select */ +#define PCIES (HWREG16(0x40004C58)) /*!< Port C Interrupt Edge Select */ +#define PCIE (HWREG16(0x40004C5A)) /*!< Port C Interrupt Enable */ +#define PCIFG (HWREG16(0x40004C5C)) /*!< Port C Interrupt Flag */ +#define P6IV (HWREG16(0x40004C5E)) /*!< Port 6 Interrupt Vector Register */ +#define PDIN (HWREG16(0x40004C60)) /*!< Port D Input */ +#define PDOUT (HWREG16(0x40004C62)) /*!< Port D Output */ +#define PDDIR (HWREG16(0x40004C64)) /*!< Port D Direction */ +#define PDREN (HWREG16(0x40004C66)) /*!< Port D Resistor Enable */ +#define PDDS (HWREG16(0x40004C68)) /*!< Port D Drive Strength */ +#define PDSEL0 (HWREG16(0x40004C6A)) /*!< Port D Select 0 */ +#define PDSEL1 (HWREG16(0x40004C6C)) /*!< Port D Select 1 */ +#define P7IV (HWREG16(0x40004C6E)) /*!< Port 7 Interrupt Vector Register */ +#define PDSELC (HWREG16(0x40004C76)) /*!< Port D Complement Select */ +#define PDIES (HWREG16(0x40004C78)) /*!< Port D Interrupt Edge Select */ +#define PDIE (HWREG16(0x40004C7A)) /*!< Port D Interrupt Enable */ +#define PDIFG (HWREG16(0x40004C7C)) /*!< Port D Interrupt Flag */ +#define P8IV (HWREG16(0x40004C7E)) /*!< Port 8 Interrupt Vector Register */ +#define PEIN (HWREG16(0x40004C80)) /*!< Port E Input */ +#define PEOUT (HWREG16(0x40004C82)) /*!< Port E Output */ +#define PEDIR (HWREG16(0x40004C84)) /*!< Port E Direction */ +#define PEREN (HWREG16(0x40004C86)) /*!< Port E Resistor Enable */ +#define PEDS (HWREG16(0x40004C88)) /*!< Port E Drive Strength */ +#define PESEL0 (HWREG16(0x40004C8A)) /*!< Port E Select 0 */ +#define PESEL1 (HWREG16(0x40004C8C)) /*!< Port E Select 1 */ +#define P9IV (HWREG16(0x40004C8E)) /*!< Port 9 Interrupt Vector Register */ +#define PESELC (HWREG16(0x40004C96)) /*!< Port E Complement Select */ +#define PEIES (HWREG16(0x40004C98)) /*!< Port E Interrupt Edge Select */ +#define PEIE (HWREG16(0x40004C9A)) /*!< Port E Interrupt Enable */ +#define PEIFG (HWREG16(0x40004C9C)) /*!< Port E Interrupt Flag */ +#define P10IV (HWREG16(0x40004C9E)) /*!< Port 10 Interrupt Vector Register */ +#define PJIN (HWREG16(0x40004D20)) /*!< Port J Input */ +#define PJOUT (HWREG16(0x40004D22)) /*!< Port J Output */ +#define PJDIR (HWREG16(0x40004D24)) /*!< Port J Direction */ +#define PJREN (HWREG16(0x40004D26)) /*!< Port J Resistor Enable */ +#define PJDS (HWREG16(0x40004D28)) /*!< Port J Drive Strength */ +#define PJSEL0 (HWREG16(0x40004D2A)) /*!< Port J Select 0 */ +#define PJSEL1 (HWREG16(0x40004D2C)) /*!< Port J Select 1 */ +#define PJSELC (HWREG16(0x40004D36)) /*!< Port J Complement Select */ +#define P1IN (HWREG8(0x40004C00)) /*!< Port 1 Input */ +#define P2IN (HWREG8(0x40004C01)) /*!< Port 2 Input */ +#define P2OUT (HWREG8(0x40004C03)) /*!< Port 2 Output */ +#define P1OUT (HWREG8(0x40004C02)) /*!< Port 1 Output */ +#define P1DIR (HWREG8(0x40004C04)) /*!< Port 1 Direction */ +#define P2DIR (HWREG8(0x40004C05)) /*!< Port 2 Direction */ +#define P1REN (HWREG8(0x40004C06)) /*!< Port 1 Resistor Enable */ +#define P2REN (HWREG8(0x40004C07)) /*!< Port 2 Resistor Enable */ +#define P1DS (HWREG8(0x40004C08)) /*!< Port 1 Drive Strength */ +#define P2DS (HWREG8(0x40004C09)) /*!< Port 2 Drive Strength */ +#define P1SEL0 (HWREG8(0x40004C0A)) /*!< Port 1 Select 0 */ +#define P2SEL0 (HWREG8(0x40004C0B)) /*!< Port 2 Select 0 */ +#define P1SEL1 (HWREG8(0x40004C0C)) /*!< Port 1 Select 1 */ +#define P2SEL1 (HWREG8(0x40004C0D)) /*!< Port 2 Select 1 */ +#define P1SELC (HWREG8(0x40004C16)) /*!< Port 1 Complement Select */ +#define P2SELC (HWREG8(0x40004C17)) /*!< Port 2 Complement Select */ +#define P1IES (HWREG8(0x40004C18)) /*!< Port 1 Interrupt Edge Select */ +#define P2IES (HWREG8(0x40004C19)) /*!< Port 2 Interrupt Edge Select */ +#define P1IE (HWREG8(0x40004C1A)) /*!< Port 1 Interrupt Enable */ +#define P2IE (HWREG8(0x40004C1B)) /*!< Port 2 Interrupt Enable */ +#define P1IFG (HWREG8(0x40004C1C)) /*!< Port 1 Interrupt Flag */ +#define P2IFG (HWREG8(0x40004C1D)) /*!< Port 2 Interrupt Flag */ +#define P3IN (HWREG8(0x40004C20)) /*!< Port 3 Input */ +#define P4IN (HWREG8(0x40004C21)) /*!< Port 4 Input */ +#define P3OUT (HWREG8(0x40004C22)) /*!< Port 3 Output */ +#define P4OUT (HWREG8(0x40004C23)) /*!< Port 4 Output */ +#define P3DIR (HWREG8(0x40004C24)) /*!< Port 3 Direction */ +#define P4DIR (HWREG8(0x40004C25)) /*!< Port 4 Direction */ +#define P3REN (HWREG8(0x40004C26)) /*!< Port 3 Resistor Enable */ +#define P4REN (HWREG8(0x40004C27)) /*!< Port 4 Resistor Enable */ +#define P3DS (HWREG8(0x40004C28)) /*!< Port 3 Drive Strength */ +#define P4DS (HWREG8(0x40004C29)) /*!< Port 4 Drive Strength */ +#define P4SEL0 (HWREG8(0x40004C2B)) /*!< Port 4 Select 0 */ +#define P3SEL0 (HWREG8(0x40004C2A)) /*!< Port 3 Select 0 */ +#define P3SEL1 (HWREG8(0x40004C2C)) /*!< Port 3 Select 1 */ +#define P4SEL1 (HWREG8(0x40004C2D)) /*!< Port 4 Select 1 */ +#define P3SELC (HWREG8(0x40004C36)) /*!< Port 3 Complement Select */ +#define P4SELC (HWREG8(0x40004C37)) /*!< Port 4 Complement Select */ +#define P3IES (HWREG8(0x40004C38)) /*!< Port 3 Interrupt Edge Select */ +#define P4IES (HWREG8(0x40004C39)) /*!< Port 4 Interrupt Edge Select */ +#define P3IE (HWREG8(0x40004C3A)) /*!< Port 3 Interrupt Enable */ +#define P4IE (HWREG8(0x40004C3B)) /*!< Port 4 Interrupt Enable */ +#define P3IFG (HWREG8(0x40004C3C)) /*!< Port 3 Interrupt Flag */ +#define P4IFG (HWREG8(0x40004C3D)) /*!< Port 4 Interrupt Flag */ +#define P5IN (HWREG8(0x40004C40)) /*!< Port 5 Input */ +#define P6IN (HWREG8(0x40004C41)) /*!< Port 6 Input */ +#define P5OUT (HWREG8(0x40004C42)) /*!< Port 5 Output */ +#define P6OUT (HWREG8(0x40004C43)) /*!< Port 6 Output */ +#define P5DIR (HWREG8(0x40004C44)) /*!< Port 5 Direction */ +#define P6DIR (HWREG8(0x40004C45)) /*!< Port 6 Direction */ +#define P5REN (HWREG8(0x40004C46)) /*!< Port 5 Resistor Enable */ +#define P6REN (HWREG8(0x40004C47)) /*!< Port 6 Resistor Enable */ +#define P5DS (HWREG8(0x40004C48)) /*!< Port 5 Drive Strength */ +#define P6DS (HWREG8(0x40004C49)) /*!< Port 6 Drive Strength */ +#define P5SEL0 (HWREG8(0x40004C4A)) /*!< Port 5 Select 0 */ +#define P6SEL0 (HWREG8(0x40004C4B)) /*!< Port 6 Select 0 */ +#define P5SEL1 (HWREG8(0x40004C4C)) /*!< Port 5 Select 1 */ +#define P6SEL1 (HWREG8(0x40004C4D)) /*!< Port 6 Select 1 */ +#define P5SELC (HWREG8(0x40004C56)) /*!< Port 5 Complement Select */ +#define P6SELC (HWREG8(0x40004C57)) /*!< Port 6 Complement Select */ +#define P5IES (HWREG8(0x40004C58)) /*!< Port 5 Interrupt Edge Select */ +#define P6IES (HWREG8(0x40004C59)) /*!< Port 6 Interrupt Edge Select */ +#define P5IE (HWREG8(0x40004C5A)) /*!< Port 5 Interrupt Enable */ +#define P6IE (HWREG8(0x40004C5B)) /*!< Port 6 Interrupt Enable */ +#define P5IFG (HWREG8(0x40004C5C)) /*!< Port 5 Interrupt Flag */ +#define P6IFG (HWREG8(0x40004C5D)) /*!< Port 6 Interrupt Flag */ +#define P7IN (HWREG8(0x40004C60)) /*!< Port 7 Input */ +#define P8IN (HWREG8(0x40004C61)) /*!< Port 8 Input */ +#define P7OUT (HWREG8(0x40004C62)) /*!< Port 7 Output */ +#define P8OUT (HWREG8(0x40004C63)) /*!< Port 8 Output */ +#define P7DIR (HWREG8(0x40004C64)) /*!< Port 7 Direction */ +#define P8DIR (HWREG8(0x40004C65)) /*!< Port 8 Direction */ +#define P7REN (HWREG8(0x40004C66)) /*!< Port 7 Resistor Enable */ +#define P8REN (HWREG8(0x40004C67)) /*!< Port 8 Resistor Enable */ +#define P7DS (HWREG8(0x40004C68)) /*!< Port 7 Drive Strength */ +#define P8DS (HWREG8(0x40004C69)) /*!< Port 8 Drive Strength */ +#define P7SEL0 (HWREG8(0x40004C6A)) /*!< Port 7 Select 0 */ +#define P8SEL0 (HWREG8(0x40004C6B)) /*!< Port 8 Select 0 */ +#define P7SEL1 (HWREG8(0x40004C6C)) /*!< Port 7 Select 1 */ +#define P8SEL1 (HWREG8(0x40004C6D)) /*!< Port 8 Select 1 */ +#define P7SELC (HWREG8(0x40004C76)) /*!< Port 7 Complement Select */ +#define P8SELC (HWREG8(0x40004C77)) /*!< Port 8 Complement Select */ +#define P7IES (HWREG8(0x40004C78)) /*!< Port 7 Interrupt Edge Select */ +#define P8IES (HWREG8(0x40004C79)) /*!< Port 8 Interrupt Edge Select */ +#define P7IE (HWREG8(0x40004C7A)) /*!< Port 7 Interrupt Enable */ +#define P8IE (HWREG8(0x40004C7B)) /*!< Port 8 Interrupt Enable */ +#define P7IFG (HWREG8(0x40004C7C)) /*!< Port 7 Interrupt Flag */ +#define P8IFG (HWREG8(0x40004C7D)) /*!< Port 8 Interrupt Flag */ +#define P9IN (HWREG8(0x40004C80)) /*!< Port 9 Input */ +#define P10IN (HWREG8(0x40004C81)) /*!< Port 10 Input */ +#define P9OUT (HWREG8(0x40004C82)) /*!< Port 9 Output */ +#define P10OUT (HWREG8(0x40004C83)) /*!< Port 10 Output */ +#define P9DIR (HWREG8(0x40004C84)) /*!< Port 9 Direction */ +#define P10DIR (HWREG8(0x40004C85)) /*!< Port 10 Direction */ +#define P9REN (HWREG8(0x40004C86)) /*!< Port 9 Resistor Enable */ +#define P10REN (HWREG8(0x40004C87)) /*!< Port 10 Resistor Enable */ +#define P9DS (HWREG8(0x40004C88)) /*!< Port 9 Drive Strength */ +#define P10DS (HWREG8(0x40004C89)) /*!< Port 10 Drive Strength */ +#define P9SEL0 (HWREG8(0x40004C8A)) /*!< Port 9 Select 0 */ +#define P10SEL0 (HWREG8(0x40004C8B)) /*!< Port 10 Select 0 */ +#define P9SEL1 (HWREG8(0x40004C8C)) /*!< Port 9 Select 1 */ +#define P10SEL1 (HWREG8(0x40004C8D)) /*!< Port 10 Select 1 */ +#define P9SELC (HWREG8(0x40004C96)) /*!< Port 9 Complement Select */ +#define P10SELC (HWREG8(0x40004C97)) /*!< Port 10 Complement Select */ +#define P9IES (HWREG8(0x40004C98)) /*!< Port 9 Interrupt Edge Select */ +#define P10IES (HWREG8(0x40004C99)) /*!< Port 10 Interrupt Edge Select */ +#define P9IE (HWREG8(0x40004C9A)) /*!< Port 9 Interrupt Enable */ +#define P10IE (HWREG8(0x40004C9B)) /*!< Port 10 Interrupt Enable */ +#define P9IFG (HWREG8(0x40004C9C)) /*!< Port 9 Interrupt Flag */ +#define P10IFG (HWREG8(0x40004C9D)) /*!< Port 10 Interrupt Flag */ + +/* Register offsets from DIO_BASE address */ +#define OFS_PAIN (0x0000) /*!< Port A Input */ +#define OFS_PAOUT (0x0002) /*!< Port A Output */ +#define OFS_PADIR (0x0004) /*!< Port A Direction */ +#define OFS_PAREN (0x0006) /*!< Port A Resistor Enable */ +#define OFS_PADS (0x0008) /*!< Port A Drive Strength */ +#define OFS_PASEL0 (0x000A) /*!< Port A Select 0 */ +#define OFS_PASEL1 (0x000C) /*!< Port A Select 1 */ +#define OFS_P1IV (0x000E) /*!< Port 1 Interrupt Vector Register */ +#define OFS_PASELC (0x0016) /*!< Port A Complement Select */ +#define OFS_PAIES (0x0018) /*!< Port A Interrupt Edge Select */ +#define OFS_PAIE (0x001A) /*!< Port A Interrupt Enable */ +#define OFS_PAIFG (0x001C) /*!< Port A Interrupt Flag */ +#define OFS_P2IV (0x001E) /*!< Port 2 Interrupt Vector Register */ +#define OFS_PBIN (0x0020) /*!< Port B Input */ +#define OFS_PBOUT (0x0022) /*!< Port B Output */ +#define OFS_PBDIR (0x0024) /*!< Port B Direction */ +#define OFS_PBREN (0x0026) /*!< Port B Resistor Enable */ +#define OFS_PBDS (0x0028) /*!< Port B Drive Strength */ +#define OFS_PBSEL0 (0x002A) /*!< Port B Select 0 */ +#define OFS_PBSEL1 (0x002C) /*!< Port B Select 1 */ +#define OFS_P3IV (0x002E) /*!< Port 3 Interrupt Vector Register */ +#define OFS_PBSELC (0x0036) /*!< Port B Complement Select */ +#define OFS_PBIES (0x0038) /*!< Port B Interrupt Edge Select */ +#define OFS_PBIE (0x003A) /*!< Port B Interrupt Enable */ +#define OFS_PBIFG (0x003C) /*!< Port B Interrupt Flag */ +#define OFS_P4IV (0x003E) /*!< Port 4 Interrupt Vector Register */ +#define OFS_PCIN (0x0040) /*!< Port C Input */ +#define OFS_PCOUT (0x0042) /*!< Port C Output */ +#define OFS_PCDIR (0x0044) /*!< Port C Direction */ +#define OFS_PCREN (0x0046) /*!< Port C Resistor Enable */ +#define OFS_PCDS (0x0048) /*!< Port C Drive Strength */ +#define OFS_PCSEL0 (0x004A) /*!< Port C Select 0 */ +#define OFS_PCSEL1 (0x004C) /*!< Port C Select 1 */ +#define OFS_P5IV (0x004E) /*!< Port 5 Interrupt Vector Register */ +#define OFS_PCSELC (0x0056) /*!< Port C Complement Select */ +#define OFS_PCIES (0x0058) /*!< Port C Interrupt Edge Select */ +#define OFS_PCIE (0x005A) /*!< Port C Interrupt Enable */ +#define OFS_PCIFG (0x005C) /*!< Port C Interrupt Flag */ +#define OFS_P6IV (0x005E) /*!< Port 6 Interrupt Vector Register */ +#define OFS_PDIN (0x0060) /*!< Port D Input */ +#define OFS_PDOUT (0x0062) /*!< Port D Output */ +#define OFS_PDDIR (0x0064) /*!< Port D Direction */ +#define OFS_PDREN (0x0066) /*!< Port D Resistor Enable */ +#define OFS_PDDS (0x0068) /*!< Port D Drive Strength */ +#define OFS_PDSEL0 (0x006A) /*!< Port D Select 0 */ +#define OFS_PDSEL1 (0x006C) /*!< Port D Select 1 */ +#define OFS_P7IV (0x006E) /*!< Port 7 Interrupt Vector Register */ +#define OFS_PDSELC (0x0076) /*!< Port D Complement Select */ +#define OFS_PDIES (0x0078) /*!< Port D Interrupt Edge Select */ +#define OFS_PDIE (0x007A) /*!< Port D Interrupt Enable */ +#define OFS_PDIFG (0x007C) /*!< Port D Interrupt Flag */ +#define OFS_P8IV (0x007E) /*!< Port 8 Interrupt Vector Register */ +#define OFS_PEIN (0x0080) /*!< Port E Input */ +#define OFS_PEOUT (0x0082) /*!< Port E Output */ +#define OFS_PEDIR (0x0084) /*!< Port E Direction */ +#define OFS_PEREN (0x0086) /*!< Port E Resistor Enable */ +#define OFS_PEDS (0x0088) /*!< Port E Drive Strength */ +#define OFS_PESEL0 (0x008A) /*!< Port E Select 0 */ +#define OFS_PESEL1 (0x008C) /*!< Port E Select 1 */ +#define OFS_P9IV (0x008E) /*!< Port 9 Interrupt Vector Register */ +#define OFS_PESELC (0x0096) /*!< Port E Complement Select */ +#define OFS_PEIES (0x0098) /*!< Port E Interrupt Edge Select */ +#define OFS_PEIE (0x009A) /*!< Port E Interrupt Enable */ +#define OFS_PEIFG (0x009C) /*!< Port E Interrupt Flag */ +#define OFS_P10IV (0x009E) /*!< Port 10 Interrupt Vector Register */ +#define OFS_PJIN (0x0120) /*!< Port J Input */ +#define OFS_PJOUT (0x0122) /*!< Port J Output */ +#define OFS_PJDIR (0x0124) /*!< Port J Direction */ +#define OFS_PJREN (0x0126) /*!< Port J Resistor Enable */ +#define OFS_PJDS (0x0128) /*!< Port J Drive Strength */ +#define OFS_PJSEL0 (0x012A) /*!< Port J Select 0 */ +#define OFS_PJSEL1 (0x012C) /*!< Port J Select 1 */ +#define OFS_PJSELC (0x0136) /*!< Port J Complement Select */ +#define OFS_P1IN (0x0000) /*!< Port 1 Input */ +#define OFS_P2IN (0x0001) /*!< Port 2 Input */ +#define OFS_P2OUT (0x0003) /*!< Port 2 Output */ +#define OFS_P1OUT (0x0002) /*!< Port 1 Output */ +#define OFS_P1DIR (0x0004) /*!< Port 1 Direction */ +#define OFS_P2DIR (0x0005) /*!< Port 2 Direction */ +#define OFS_P1REN (0x0006) /*!< Port 1 Resistor Enable */ +#define OFS_P2REN (0x0007) /*!< Port 2 Resistor Enable */ +#define OFS_P1DS (0x0008) /*!< Port 1 Drive Strength */ +#define OFS_P2DS (0x0009) /*!< Port 2 Drive Strength */ +#define OFS_P1SEL0 (0x000A) /*!< Port 1 Select 0 */ +#define OFS_P2SEL0 (0x000B) /*!< Port 2 Select 0 */ +#define OFS_P1SEL1 (0x000C) /*!< Port 1 Select 1 */ +#define OFS_P2SEL1 (0x000D) /*!< Port 2 Select 1 */ +#define OFS_P1SELC (0x0016) /*!< Port 1 Complement Select */ +#define OFS_P2SELC (0x0017) /*!< Port 2 Complement Select */ +#define OFS_P1IES (0x0018) /*!< Port 1 Interrupt Edge Select */ +#define OFS_P2IES (0x0019) /*!< Port 2 Interrupt Edge Select */ +#define OFS_P1IE (0x001A) /*!< Port 1 Interrupt Enable */ +#define OFS_P2IE (0x001B) /*!< Port 2 Interrupt Enable */ +#define OFS_P1IFG (0x001C) /*!< Port 1 Interrupt Flag */ +#define OFS_P2IFG (0x001D) /*!< Port 2 Interrupt Flag */ +#define OFS_P3IN (0x0020) /*!< Port 3 Input */ +#define OFS_P4IN (0x0021) /*!< Port 4 Input */ +#define OFS_P3OUT (0x0022) /*!< Port 3 Output */ +#define OFS_P4OUT (0x0023) /*!< Port 4 Output */ +#define OFS_P3DIR (0x0024) /*!< Port 3 Direction */ +#define OFS_P4DIR (0x0025) /*!< Port 4 Direction */ +#define OFS_P3REN (0x0026) /*!< Port 3 Resistor Enable */ +#define OFS_P4REN (0x0027) /*!< Port 4 Resistor Enable */ +#define OFS_P3DS (0x0028) /*!< Port 3 Drive Strength */ +#define OFS_P4DS (0x0029) /*!< Port 4 Drive Strength */ +#define OFS_P4SEL0 (0x002B) /*!< Port 4 Select 0 */ +#define OFS_P3SEL0 (0x002A) /*!< Port 3 Select 0 */ +#define OFS_P3SEL1 (0x002C) /*!< Port 3 Select 1 */ +#define OFS_P4SEL1 (0x002D) /*!< Port 4 Select 1 */ +#define OFS_P3SELC (0x0036) /*!< Port 3 Complement Select */ +#define OFS_P4SELC (0x0037) /*!< Port 4 Complement Select */ +#define OFS_P3IES (0x0038) /*!< Port 3 Interrupt Edge Select */ +#define OFS_P4IES (0x0039) /*!< Port 4 Interrupt Edge Select */ +#define OFS_P3IE (0x003A) /*!< Port 3 Interrupt Enable */ +#define OFS_P4IE (0x003B) /*!< Port 4 Interrupt Enable */ +#define OFS_P3IFG (0x003C) /*!< Port 3 Interrupt Flag */ +#define OFS_P4IFG (0x003D) /*!< Port 4 Interrupt Flag */ +#define OFS_P5IN (0x0040) /*!< Port 5 Input */ +#define OFS_P6IN (0x0041) /*!< Port 6 Input */ +#define OFS_P5OUT (0x0042) /*!< Port 5 Output */ +#define OFS_P6OUT (0x0043) /*!< Port 6 Output */ +#define OFS_P5DIR (0x0044) /*!< Port 5 Direction */ +#define OFS_P6DIR (0x0045) /*!< Port 6 Direction */ +#define OFS_P5REN (0x0046) /*!< Port 5 Resistor Enable */ +#define OFS_P6REN (0x0047) /*!< Port 6 Resistor Enable */ +#define OFS_P5DS (0x0048) /*!< Port 5 Drive Strength */ +#define OFS_P6DS (0x0049) /*!< Port 6 Drive Strength */ +#define OFS_P5SEL0 (0x004A) /*!< Port 5 Select 0 */ +#define OFS_P6SEL0 (0x004B) /*!< Port 6 Select 0 */ +#define OFS_P5SEL1 (0x004C) /*!< Port 5 Select 1 */ +#define OFS_P6SEL1 (0x004D) /*!< Port 6 Select 1 */ +#define OFS_P5SELC (0x0056) /*!< Port 5 Complement Select */ +#define OFS_P6SELC (0x0057) /*!< Port 6 Complement Select */ +#define OFS_P5IES (0x0058) /*!< Port 5 Interrupt Edge Select */ +#define OFS_P6IES (0x0059) /*!< Port 6 Interrupt Edge Select */ +#define OFS_P5IE (0x005A) /*!< Port 5 Interrupt Enable */ +#define OFS_P6IE (0x005B) /*!< Port 6 Interrupt Enable */ +#define OFS_P5IFG (0x005C) /*!< Port 5 Interrupt Flag */ +#define OFS_P6IFG (0x005D) /*!< Port 6 Interrupt Flag */ +#define OFS_P7IN (0x0060) /*!< Port 7 Input */ +#define OFS_P8IN (0x0061) /*!< Port 8 Input */ +#define OFS_P7OUT (0x0062) /*!< Port 7 Output */ +#define OFS_P8OUT (0x0063) /*!< Port 8 Output */ +#define OFS_P7DIR (0x0064) /*!< Port 7 Direction */ +#define OFS_P8DIR (0x0065) /*!< Port 8 Direction */ +#define OFS_P7REN (0x0066) /*!< Port 7 Resistor Enable */ +#define OFS_P8REN (0x0067) /*!< Port 8 Resistor Enable */ +#define OFS_P7DS (0x0068) /*!< Port 7 Drive Strength */ +#define OFS_P8DS (0x0069) /*!< Port 8 Drive Strength */ +#define OFS_P7SEL0 (0x006A) /*!< Port 7 Select 0 */ +#define OFS_P8SEL0 (0x006B) /*!< Port 8 Select 0 */ +#define OFS_P7SEL1 (0x006C) /*!< Port 7 Select 1 */ +#define OFS_P8SEL1 (0x006D) /*!< Port 8 Select 1 */ +#define OFS_P7SELC (0x0076) /*!< Port 7 Complement Select */ +#define OFS_P8SELC (0x0077) /*!< Port 8 Complement Select */ +#define OFS_P7IES (0x0078) /*!< Port 7 Interrupt Edge Select */ +#define OFS_P8IES (0x0079) /*!< Port 8 Interrupt Edge Select */ +#define OFS_P7IE (0x007A) /*!< Port 7 Interrupt Enable */ +#define OFS_P8IE (0x007B) /*!< Port 8 Interrupt Enable */ +#define OFS_P7IFG (0x007C) /*!< Port 7 Interrupt Flag */ +#define OFS_P8IFG (0x007D) /*!< Port 8 Interrupt Flag */ +#define OFS_P9IN (0x0080) /*!< Port 9 Input */ +#define OFS_P10IN (0x0081) /*!< Port 10 Input */ +#define OFS_P9OUT (0x0082) /*!< Port 9 Output */ +#define OFS_P10OUT (0x0083) /*!< Port 10 Output */ +#define OFS_P9DIR (0x0084) /*!< Port 9 Direction */ +#define OFS_P10DIR (0x0085) /*!< Port 10 Direction */ +#define OFS_P9REN (0x0086) /*!< Port 9 Resistor Enable */ +#define OFS_P10REN (0x0087) /*!< Port 10 Resistor Enable */ +#define OFS_P9DS (0x0088) /*!< Port 9 Drive Strength */ +#define OFS_P10DS (0x0089) /*!< Port 10 Drive Strength */ +#define OFS_P9SEL0 (0x008A) /*!< Port 9 Select 0 */ +#define OFS_P10SEL0 (0x008B) /*!< Port 10 Select 0 */ +#define OFS_P9SEL1 (0x008C) /*!< Port 9 Select 1 */ +#define OFS_P10SEL1 (0x008D) /*!< Port 10 Select 1 */ +#define OFS_P9SELC (0x0096) /*!< Port 9 Complement Select */ +#define OFS_P10SELC (0x0097) /*!< Port 10 Complement Select */ +#define OFS_P9IES (0x0098) /*!< Port 9 Interrupt Edge Select */ +#define OFS_P10IES (0x0099) /*!< Port 10 Interrupt Edge Select */ +#define OFS_P9IE (0x009A) /*!< Port 9 Interrupt Enable */ +#define OFS_P10IE (0x009B) /*!< Port 10 Interrupt Enable */ +#define OFS_P9IFG (0x009C) /*!< Port 9 Interrupt Flag */ +#define OFS_P10IFG (0x009D) /*!< Port 10 Interrupt Flag */ + + +/****************************************************************************** +* EUSCI_A0 Registers +******************************************************************************/ +#define UCA0CTLW0 (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */ +#define UCA0CTLW0_SPI (HWREG16(0x40001000)) +#define UCA0CTLW1 (HWREG16(0x40001002)) /*!< eUSCI_Ax Control Word Register 1 */ +#define UCA0BRW (HWREG16(0x40001006)) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define UCA0BRW_SPI (HWREG16(0x40001006)) +#define UCA0MCTLW (HWREG16(0x40001008)) /*!< eUSCI_Ax Modulation Control Word Register */ +#define UCA0STATW (HWREG16(0x4000100A)) /*!< eUSCI_Ax Status Register */ +#define UCA0STATW_SPI (HWREG16(0x4000100A)) +#define UCA0RXBUF (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */ +#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) +#define UCA0TXBUF (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */ +#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) +#define UCA0ABCTL (HWREG16(0x40001010)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define UCA0IRCTL (HWREG16(0x40001012)) /*!< eUSCI_Ax IrDA Control Word Register */ +#define UCA0IE (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */ +#define UCA0IE_SPI (HWREG16(0x4000101A)) +#define UCA0IFG (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */ +#define UCA0IFG_SPI (HWREG16(0x4000101C)) +#define UCA0IV (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */ +#define UCA0IV_SPI (HWREG16(0x4000101E)) + +/* Register offsets from EUSCI_A0_BASE address */ +#define OFS_UCA0CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ +#define OFS_UCA0CTLW0_SPI (0x0000) +#define OFS_UCA0CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ +#define OFS_UCA0BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define OFS_UCA0BRW_SPI (0x0006) +#define OFS_UCA0MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ +#define OFS_UCA0STATW (0x000A) /*!< eUSCI_Ax Status Register */ +#define OFS_UCA0STATW_SPI (0x000A) +#define OFS_UCA0RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ +#define OFS_UCA0RXBUF_SPI (0x000C) +#define OFS_UCA0TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ +#define OFS_UCA0TXBUF_SPI (0x000E) +#define OFS_UCA0ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define OFS_UCA0IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ +#define OFS_UCA0IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ +#define OFS_UCA0IE_SPI (0x001A) +#define OFS_UCA0IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ +#define OFS_UCA0IFG_SPI (0x001C) +#define OFS_UCA0IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ +#define OFS_UCA0IV_SPI (0x001E) + +#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */ +#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */ +#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */ +#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */ +#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ +#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */ + +/****************************************************************************** +* EUSCI_A1 Registers +******************************************************************************/ +#define UCA1CTLW0 (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */ +#define UCA1CTLW0_SPI (HWREG16(0x40001400)) +#define UCA1CTLW1 (HWREG16(0x40001402)) /*!< eUSCI_Ax Control Word Register 1 */ +#define UCA1BRW (HWREG16(0x40001406)) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define UCA1BRW_SPI (HWREG16(0x40001406)) +#define UCA1MCTLW (HWREG16(0x40001408)) /*!< eUSCI_Ax Modulation Control Word Register */ +#define UCA1STATW (HWREG16(0x4000140A)) /*!< eUSCI_Ax Status Register */ +#define UCA1STATW_SPI (HWREG16(0x4000140A)) +#define UCA1RXBUF (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */ +#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) +#define UCA1TXBUF (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */ +#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) +#define UCA1ABCTL (HWREG16(0x40001410)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define UCA1IRCTL (HWREG16(0x40001412)) /*!< eUSCI_Ax IrDA Control Word Register */ +#define UCA1IE (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */ +#define UCA1IE_SPI (HWREG16(0x4000141A)) +#define UCA1IFG (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */ +#define UCA1IFG_SPI (HWREG16(0x4000141C)) +#define UCA1IV (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */ +#define UCA1IV_SPI (HWREG16(0x4000141E)) + +/* Register offsets from EUSCI_A1_BASE address */ +#define OFS_UCA1CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ +#define OFS_UCA1CTLW0_SPI (0x0000) +#define OFS_UCA1CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ +#define OFS_UCA1BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define OFS_UCA1BRW_SPI (0x0006) +#define OFS_UCA1MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ +#define OFS_UCA1STATW (0x000A) /*!< eUSCI_Ax Status Register */ +#define OFS_UCA1STATW_SPI (0x000A) +#define OFS_UCA1RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ +#define OFS_UCA1RXBUF_SPI (0x000C) +#define OFS_UCA1TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ +#define OFS_UCA1TXBUF_SPI (0x000E) +#define OFS_UCA1ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define OFS_UCA1IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ +#define OFS_UCA1IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ +#define OFS_UCA1IE_SPI (0x001A) +#define OFS_UCA1IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ +#define OFS_UCA1IFG_SPI (0x001C) +#define OFS_UCA1IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ +#define OFS_UCA1IV_SPI (0x001E) + +#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */ +#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */ +#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */ +#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */ +#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ +#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */ + +/****************************************************************************** +* EUSCI_A2 Registers +******************************************************************************/ +#define UCA2CTLW0 (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */ +#define UCA2CTLW0_SPI (HWREG16(0x40001800)) +#define UCA2CTLW1 (HWREG16(0x40001802)) /*!< eUSCI_Ax Control Word Register 1 */ +#define UCA2BRW (HWREG16(0x40001806)) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define UCA2BRW_SPI (HWREG16(0x40001806)) +#define UCA2MCTLW (HWREG16(0x40001808)) /*!< eUSCI_Ax Modulation Control Word Register */ +#define UCA2STATW (HWREG16(0x4000180A)) /*!< eUSCI_Ax Status Register */ +#define UCA2STATW_SPI (HWREG16(0x4000180A)) +#define UCA2RXBUF (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */ +#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) +#define UCA2TXBUF (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */ +#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) +#define UCA2ABCTL (HWREG16(0x40001810)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define UCA2IRCTL (HWREG16(0x40001812)) /*!< eUSCI_Ax IrDA Control Word Register */ +#define UCA2IE (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */ +#define UCA2IE_SPI (HWREG16(0x4000181A)) +#define UCA2IFG (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */ +#define UCA2IFG_SPI (HWREG16(0x4000181C)) +#define UCA2IV (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */ +#define UCA2IV_SPI (HWREG16(0x4000181E)) + +/* Register offsets from EUSCI_A2_BASE address */ +#define OFS_UCA2CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ +#define OFS_UCA2CTLW0_SPI (0x0000) +#define OFS_UCA2CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ +#define OFS_UCA2BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define OFS_UCA2BRW_SPI (0x0006) +#define OFS_UCA2MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ +#define OFS_UCA2STATW (0x000A) /*!< eUSCI_Ax Status Register */ +#define OFS_UCA2STATW_SPI (0x000A) +#define OFS_UCA2RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ +#define OFS_UCA2RXBUF_SPI (0x000C) +#define OFS_UCA2TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ +#define OFS_UCA2TXBUF_SPI (0x000E) +#define OFS_UCA2ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define OFS_UCA2IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ +#define OFS_UCA2IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ +#define OFS_UCA2IE_SPI (0x001A) +#define OFS_UCA2IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ +#define OFS_UCA2IFG_SPI (0x001C) +#define OFS_UCA2IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ +#define OFS_UCA2IV_SPI (0x001E) + +#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */ +#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */ +#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */ +#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */ +#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ +#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */ + +/****************************************************************************** +* EUSCI_A3 Registers +******************************************************************************/ +#define UCA3CTLW0 (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */ +#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) +#define UCA3CTLW1 (HWREG16(0x40001C02)) /*!< eUSCI_Ax Control Word Register 1 */ +#define UCA3BRW (HWREG16(0x40001C06)) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define UCA3BRW_SPI (HWREG16(0x40001C06)) +#define UCA3MCTLW (HWREG16(0x40001C08)) /*!< eUSCI_Ax Modulation Control Word Register */ +#define UCA3STATW (HWREG16(0x40001C0A)) /*!< eUSCI_Ax Status Register */ +#define UCA3STATW_SPI (HWREG16(0x40001C0A)) +#define UCA3RXBUF (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */ +#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) +#define UCA3TXBUF (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */ +#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) +#define UCA3ABCTL (HWREG16(0x40001C10)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define UCA3IRCTL (HWREG16(0x40001C12)) /*!< eUSCI_Ax IrDA Control Word Register */ +#define UCA3IE (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */ +#define UCA3IE_SPI (HWREG16(0x40001C1A)) +#define UCA3IFG (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */ +#define UCA3IFG_SPI (HWREG16(0x40001C1C)) +#define UCA3IV (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */ +#define UCA3IV_SPI (HWREG16(0x40001C1E)) + +/* Register offsets from EUSCI_A3_BASE address */ +#define OFS_UCA3CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ +#define OFS_UCA3CTLW0_SPI (0x0000) +#define OFS_UCA3CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ +#define OFS_UCA3BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ +#define OFS_UCA3BRW_SPI (0x0006) +#define OFS_UCA3MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ +#define OFS_UCA3STATW (0x000A) /*!< eUSCI_Ax Status Register */ +#define OFS_UCA3STATW_SPI (0x000A) +#define OFS_UCA3RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ +#define OFS_UCA3RXBUF_SPI (0x000C) +#define OFS_UCA3TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ +#define OFS_UCA3TXBUF_SPI (0x000E) +#define OFS_UCA3ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ +#define OFS_UCA3IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ +#define OFS_UCA3IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ +#define OFS_UCA3IE_SPI (0x001A) +#define OFS_UCA3IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ +#define OFS_UCA3IFG_SPI (0x001C) +#define OFS_UCA3IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ +#define OFS_UCA3IV_SPI (0x001E) + +#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */ +#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */ +#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */ +#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */ +#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ +#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */ + +/****************************************************************************** +* EUSCI_B0 Registers +******************************************************************************/ +#define UCB0CTLW0 (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */ +#define UCB0CTLW0_SPI (HWREG16(0x40002000)) +#define UCB0CTLW1 (HWREG16(0x40002002)) /*!< eUSCI_Bx Control Word Register 1 */ +#define UCB0BRW (HWREG16(0x40002006)) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define UCB0BRW_SPI (HWREG16(0x40002006)) +#define UCB0STATW (HWREG16(0x40002008)) /*!< eUSCI_Bx Status Register */ +#define UCB0STATW_SPI (HWREG16(0x40002008)) +#define UCB0TBCNT (HWREG16(0x4000200A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define UCB0RXBUF (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */ +#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) +#define UCB0TXBUF (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */ +#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) +#define UCB0I2COA0 (HWREG16(0x40002014)) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define UCB0I2COA1 (HWREG16(0x40002016)) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define UCB0I2COA2 (HWREG16(0x40002018)) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define UCB0I2COA3 (HWREG16(0x4000201A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define UCB0ADDRX (HWREG16(0x4000201C)) /*!< eUSCI_Bx I2C Received Address Register */ +#define UCB0ADDMASK (HWREG16(0x4000201E)) /*!< eUSCI_Bx I2C Address Mask Register */ +#define UCB0I2CSA (HWREG16(0x40002020)) /*!< eUSCI_Bx I2C Slave Address Register */ +#define UCB0IE (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */ +#define UCB0IE_SPI (HWREG16(0x4000202A)) +#define UCB0IFG (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */ +#define UCB0IFG_SPI (HWREG16(0x4000202C)) +#define UCB0IV (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */ +#define UCB0IV_SPI (HWREG16(0x4000202E)) + +/* Register offsets from EUSCI_B0_BASE address */ +#define OFS_UCB0CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ +#define OFS_UCB0CTLW0_SPI (0x0000) +#define OFS_UCB0CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ +#define OFS_UCB0BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define OFS_UCB0BRW_SPI (0x0006) +#define OFS_UCB0STATW (0x0008) /*!< eUSCI_Bx Status Register */ +#define OFS_UCB0STATW_SPI (0x0008) +#define OFS_UCB0TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define OFS_UCB0RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ +#define OFS_UCB0RXBUF_SPI (0x000C) +#define OFS_UCB0TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ +#define OFS_UCB0TXBUF_SPI (0x000E) +#define OFS_UCB0I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define OFS_UCB0I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define OFS_UCB0I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define OFS_UCB0I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define OFS_UCB0ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ +#define OFS_UCB0ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ +#define OFS_UCB0I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ +#define OFS_UCB0IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ +#define OFS_UCB0IE_SPI (0x002A) +#define OFS_UCB0IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ +#define OFS_UCB0IFG_SPI (0x002C) +#define OFS_UCB0IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ +#define OFS_UCB0IV_SPI (0x002E) + +#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */ +#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */ +#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */ +#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */ +#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */ +#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */ + +/****************************************************************************** +* EUSCI_B1 Registers +******************************************************************************/ +#define UCB1CTLW0 (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */ +#define UCB1CTLW0_SPI (HWREG16(0x40002400)) +#define UCB1CTLW1 (HWREG16(0x40002402)) /*!< eUSCI_Bx Control Word Register 1 */ +#define UCB1BRW (HWREG16(0x40002406)) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define UCB1BRW_SPI (HWREG16(0x40002406)) +#define UCB1STATW (HWREG16(0x40002408)) /*!< eUSCI_Bx Status Register */ +#define UCB1STATW_SPI (HWREG16(0x40002408)) +#define UCB1TBCNT (HWREG16(0x4000240A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define UCB1RXBUF (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */ +#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) +#define UCB1TXBUF (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */ +#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) +#define UCB1I2COA0 (HWREG16(0x40002414)) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define UCB1I2COA1 (HWREG16(0x40002416)) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define UCB1I2COA2 (HWREG16(0x40002418)) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define UCB1I2COA3 (HWREG16(0x4000241A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define UCB1ADDRX (HWREG16(0x4000241C)) /*!< eUSCI_Bx I2C Received Address Register */ +#define UCB1ADDMASK (HWREG16(0x4000241E)) /*!< eUSCI_Bx I2C Address Mask Register */ +#define UCB1I2CSA (HWREG16(0x40002420)) /*!< eUSCI_Bx I2C Slave Address Register */ +#define UCB1IE (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */ +#define UCB1IE_SPI (HWREG16(0x4000242A)) +#define UCB1IFG (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */ +#define UCB1IFG_SPI (HWREG16(0x4000242C)) +#define UCB1IV (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */ +#define UCB1IV_SPI (HWREG16(0x4000242E)) + +/* Register offsets from EUSCI_B1_BASE address */ +#define OFS_UCB1CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ +#define OFS_UCB1CTLW0_SPI (0x0000) +#define OFS_UCB1CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ +#define OFS_UCB1BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define OFS_UCB1BRW_SPI (0x0006) +#define OFS_UCB1STATW (0x0008) /*!< eUSCI_Bx Status Register */ +#define OFS_UCB1STATW_SPI (0x0008) +#define OFS_UCB1TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define OFS_UCB1RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ +#define OFS_UCB1RXBUF_SPI (0x000C) +#define OFS_UCB1TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ +#define OFS_UCB1TXBUF_SPI (0x000E) +#define OFS_UCB1I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define OFS_UCB1I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define OFS_UCB1I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define OFS_UCB1I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define OFS_UCB1ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ +#define OFS_UCB1ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ +#define OFS_UCB1I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ +#define OFS_UCB1IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ +#define OFS_UCB1IE_SPI (0x002A) +#define OFS_UCB1IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ +#define OFS_UCB1IFG_SPI (0x002C) +#define OFS_UCB1IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ +#define OFS_UCB1IV_SPI (0x002E) + +#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */ +#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */ +#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */ +#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */ +#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */ +#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */ + +/****************************************************************************** +* EUSCI_B2 Registers +******************************************************************************/ +#define UCB2CTLW0 (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */ +#define UCB2CTLW0_SPI (HWREG16(0x40002800)) +#define UCB2CTLW1 (HWREG16(0x40002802)) /*!< eUSCI_Bx Control Word Register 1 */ +#define UCB2BRW (HWREG16(0x40002806)) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define UCB2BRW_SPI (HWREG16(0x40002806)) +#define UCB2STATW (HWREG16(0x40002808)) /*!< eUSCI_Bx Status Register */ +#define UCB2STATW_SPI (HWREG16(0x40002808)) +#define UCB2TBCNT (HWREG16(0x4000280A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define UCB2RXBUF (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */ +#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) +#define UCB2TXBUF (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */ +#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) +#define UCB2I2COA0 (HWREG16(0x40002814)) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define UCB2I2COA1 (HWREG16(0x40002816)) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define UCB2I2COA2 (HWREG16(0x40002818)) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define UCB2I2COA3 (HWREG16(0x4000281A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define UCB2ADDRX (HWREG16(0x4000281C)) /*!< eUSCI_Bx I2C Received Address Register */ +#define UCB2ADDMASK (HWREG16(0x4000281E)) /*!< eUSCI_Bx I2C Address Mask Register */ +#define UCB2I2CSA (HWREG16(0x40002820)) /*!< eUSCI_Bx I2C Slave Address Register */ +#define UCB2IE (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */ +#define UCB2IE_SPI (HWREG16(0x4000282A)) +#define UCB2IFG (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */ +#define UCB2IFG_SPI (HWREG16(0x4000282C)) +#define UCB2IV (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */ +#define UCB2IV_SPI (HWREG16(0x4000282E)) + +/* Register offsets from EUSCI_B2_BASE address */ +#define OFS_UCB2CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ +#define OFS_UCB2CTLW0_SPI (0x0000) +#define OFS_UCB2CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ +#define OFS_UCB2BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define OFS_UCB2BRW_SPI (0x0006) +#define OFS_UCB2STATW (0x0008) /*!< eUSCI_Bx Status Register */ +#define OFS_UCB2STATW_SPI (0x0008) +#define OFS_UCB2TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define OFS_UCB2RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ +#define OFS_UCB2RXBUF_SPI (0x000C) +#define OFS_UCB2TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ +#define OFS_UCB2TXBUF_SPI (0x000E) +#define OFS_UCB2I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define OFS_UCB2I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define OFS_UCB2I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define OFS_UCB2I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define OFS_UCB2ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ +#define OFS_UCB2ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ +#define OFS_UCB2I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ +#define OFS_UCB2IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ +#define OFS_UCB2IE_SPI (0x002A) +#define OFS_UCB2IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ +#define OFS_UCB2IFG_SPI (0x002C) +#define OFS_UCB2IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ +#define OFS_UCB2IV_SPI (0x002E) + +#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */ +#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */ +#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */ +#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */ +#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */ +#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */ + +/****************************************************************************** +* EUSCI_B3 Registers +******************************************************************************/ +#define UCB3CTLW0 (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */ +#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) +#define UCB3CTLW1 (HWREG16(0x40002C02)) /*!< eUSCI_Bx Control Word Register 1 */ +#define UCB3BRW (HWREG16(0x40002C06)) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define UCB3BRW_SPI (HWREG16(0x40002C06)) +#define UCB3STATW (HWREG16(0x40002C08)) /*!< eUSCI_Bx Status Register */ +#define UCB3STATW_SPI (HWREG16(0x40002C08)) +#define UCB3TBCNT (HWREG16(0x40002C0A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define UCB3RXBUF (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */ +#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) +#define UCB3TXBUF (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */ +#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) +#define UCB3I2COA0 (HWREG16(0x40002C14)) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define UCB3I2COA1 (HWREG16(0x40002C16)) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define UCB3I2COA2 (HWREG16(0x40002C18)) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define UCB3I2COA3 (HWREG16(0x40002C1A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define UCB3ADDRX (HWREG16(0x40002C1C)) /*!< eUSCI_Bx I2C Received Address Register */ +#define UCB3ADDMASK (HWREG16(0x40002C1E)) /*!< eUSCI_Bx I2C Address Mask Register */ +#define UCB3I2CSA (HWREG16(0x40002C20)) /*!< eUSCI_Bx I2C Slave Address Register */ +#define UCB3IE (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */ +#define UCB3IE_SPI (HWREG16(0x40002C2A)) +#define UCB3IFG (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */ +#define UCB3IFG_SPI (HWREG16(0x40002C2C)) +#define UCB3IV (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */ +#define UCB3IV_SPI (HWREG16(0x40002C2E)) + +/* Register offsets from EUSCI_B3_BASE address */ +#define OFS_UCB3CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ +#define OFS_UCB3CTLW0_SPI (0x0000) +#define OFS_UCB3CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ +#define OFS_UCB3BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ +#define OFS_UCB3BRW_SPI (0x0006) +#define OFS_UCB3STATW (0x0008) /*!< eUSCI_Bx Status Register */ +#define OFS_UCB3STATW_SPI (0x0008) +#define OFS_UCB3TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ +#define OFS_UCB3RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ +#define OFS_UCB3RXBUF_SPI (0x000C) +#define OFS_UCB3TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ +#define OFS_UCB3TXBUF_SPI (0x000E) +#define OFS_UCB3I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ +#define OFS_UCB3I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ +#define OFS_UCB3I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ +#define OFS_UCB3I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ +#define OFS_UCB3ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ +#define OFS_UCB3ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ +#define OFS_UCB3I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ +#define OFS_UCB3IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ +#define OFS_UCB3IE_SPI (0x002A) +#define OFS_UCB3IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ +#define OFS_UCB3IFG_SPI (0x002C) +#define OFS_UCB3IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ +#define OFS_UCB3IV_SPI (0x002E) + +#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */ +#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */ +#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */ +#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */ +#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */ +#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */ + +/****************************************************************************** +* PMAP Registers +******************************************************************************/ +#define PMAPKEYID (HWREG16(0x40005000)) /*!< Port Mapping Key Register */ +#define PMAPCTL (HWREG16(0x40005002)) /*!< Port Mapping Control Register */ +#define P1MAP01 (HWREG16(0x40005008)) /*!< Port mapping register, P1.0 and P1.1 */ +#define P1MAP23 (HWREG16(0x4000500A)) /*!< Port mapping register, P1.2 and P1.3 */ +#define P1MAP45 (HWREG16(0x4000500C)) /*!< Port mapping register, P1.4 and P1.5 */ +#define P1MAP67 (HWREG16(0x4000500E)) /*!< Port mapping register, P1.6 and P1.7 */ +#define P2MAP01 (HWREG16(0x40005010)) /*!< Port mapping register, P2.0 and P2.1 */ +#define P2MAP23 (HWREG16(0x40005012)) /*!< Port mapping register, P2.2 and P2.3 */ +#define P2MAP45 (HWREG16(0x40005014)) /*!< Port mapping register, P2.4 and P2.5 */ +#define P2MAP67 (HWREG16(0x40005016)) /*!< Port mapping register, P2.6 and P2.7 */ +#define P3MAP01 (HWREG16(0x40005018)) /*!< Port mapping register, P3.0 and P3.1 */ +#define P3MAP23 (HWREG16(0x4000501A)) /*!< Port mapping register, P3.2 and P3.3 */ +#define P3MAP45 (HWREG16(0x4000501C)) /*!< Port mapping register, P3.4 and P3.5 */ +#define P3MAP67 (HWREG16(0x4000501E)) /*!< Port mapping register, P3.6 and P3.7 */ +#define P4MAP01 (HWREG16(0x40005020)) /*!< Port mapping register, P4.0 and P4.1 */ +#define P4MAP23 (HWREG16(0x40005022)) /*!< Port mapping register, P4.2 and P4.3 */ +#define P4MAP45 (HWREG16(0x40005024)) /*!< Port mapping register, P4.4 and P4.5 */ +#define P4MAP67 (HWREG16(0x40005026)) /*!< Port mapping register, P4.6 and P4.7 */ +#define P5MAP01 (HWREG16(0x40005028)) /*!< Port mapping register, P5.0 and P5.1 */ +#define P5MAP23 (HWREG16(0x4000502A)) /*!< Port mapping register, P5.2 and P5.3 */ +#define P5MAP45 (HWREG16(0x4000502C)) /*!< Port mapping register, P5.4 and P5.5 */ +#define P5MAP67 (HWREG16(0x4000502E)) /*!< Port mapping register, P5.6 and P5.7 */ +#define P6MAP01 (HWREG16(0x40005030)) /*!< Port mapping register, P6.0 and P6.1 */ +#define P6MAP23 (HWREG16(0x40005032)) /*!< Port mapping register, P6.2 and P6.3 */ +#define P6MAP45 (HWREG16(0x40005034)) /*!< Port mapping register, P6.4 and P6.5 */ +#define P6MAP67 (HWREG16(0x40005036)) /*!< Port mapping register, P6.6 and P6.7 */ +#define P7MAP01 (HWREG16(0x40005038)) /*!< Port mapping register, P7.0 and P7.1 */ +#define P7MAP23 (HWREG16(0x4000503A)) /*!< Port mapping register, P7.2 and P7.3 */ +#define P7MAP45 (HWREG16(0x4000503C)) /*!< Port mapping register, P7.4 and P7.5 */ +#define P7MAP67 (HWREG16(0x4000503E)) /*!< Port mapping register, P7.6 and P7.7 */ + +/* Register offsets from PMAP_BASE address */ +#define OFS_PMAPKEYID (0x0000) /*!< Port Mapping Key Register */ +#define OFS_PMAPCTL (0x0002) /*!< Port Mapping Control Register */ +#define OFS_P1MAP01 (0x0008) /*!< Port mapping register, P1.0 and P1.1 */ +#define OFS_P1MAP23 (0x000A) /*!< Port mapping register, P1.2 and P1.3 */ +#define OFS_P1MAP45 (0x000C) /*!< Port mapping register, P1.4 and P1.5 */ +#define OFS_P1MAP67 (0x000E) /*!< Port mapping register, P1.6 and P1.7 */ +#define OFS_P2MAP01 (0x0010) /*!< Port mapping register, P2.0 and P2.1 */ +#define OFS_P2MAP23 (0x0012) /*!< Port mapping register, P2.2 and P2.3 */ +#define OFS_P2MAP45 (0x0014) /*!< Port mapping register, P2.4 and P2.5 */ +#define OFS_P2MAP67 (0x0016) /*!< Port mapping register, P2.6 and P2.7 */ +#define OFS_P3MAP01 (0x0018) /*!< Port mapping register, P3.0 and P3.1 */ +#define OFS_P3MAP23 (0x001A) /*!< Port mapping register, P3.2 and P3.3 */ +#define OFS_P3MAP45 (0x001C) /*!< Port mapping register, P3.4 and P3.5 */ +#define OFS_P3MAP67 (0x001E) /*!< Port mapping register, P3.6 and P3.7 */ +#define OFS_P4MAP01 (0x0020) /*!< Port mapping register, P4.0 and P4.1 */ +#define OFS_P4MAP23 (0x0022) /*!< Port mapping register, P4.2 and P4.3 */ +#define OFS_P4MAP45 (0x0024) /*!< Port mapping register, P4.4 and P4.5 */ +#define OFS_P4MAP67 (0x0026) /*!< Port mapping register, P4.6 and P4.7 */ +#define OFS_P5MAP01 (0x0028) /*!< Port mapping register, P5.0 and P5.1 */ +#define OFS_P5MAP23 (0x002A) /*!< Port mapping register, P5.2 and P5.3 */ +#define OFS_P5MAP45 (0x002C) /*!< Port mapping register, P5.4 and P5.5 */ +#define OFS_P5MAP67 (0x002E) /*!< Port mapping register, P5.6 and P5.7 */ +#define OFS_P6MAP01 (0x0030) /*!< Port mapping register, P6.0 and P6.1 */ +#define OFS_P6MAP23 (0x0032) /*!< Port mapping register, P6.2 and P6.3 */ +#define OFS_P6MAP45 (0x0034) /*!< Port mapping register, P6.4 and P6.5 */ +#define OFS_P6MAP67 (0x0036) /*!< Port mapping register, P6.6 and P6.7 */ +#define OFS_P7MAP01 (0x0038) /*!< Port mapping register, P7.0 and P7.1 */ +#define OFS_P7MAP23 (0x003A) /*!< Port mapping register, P7.2 and P7.3 */ +#define OFS_P7MAP45 (0x003C) /*!< Port mapping register, P7.4 and P7.5 */ +#define OFS_P7MAP67 (0x003E) /*!< Port mapping register, P7.6 and P7.7 */ + + +/****************************************************************************** +* REF_A Registers +******************************************************************************/ +#define REFCTL0 (HWREG16(0x40003000)) /*!< REF Control Register 0 */ + +/* Register offsets from REF_A_BASE address */ +#define OFS_REFCTL0 (0x0000) /*!< REF Control Register 0 */ + +#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */ +#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */ + +/****************************************************************************** +* RTC_C Registers +******************************************************************************/ +#define RTCCTL0 (HWREG16(0x40004400)) /*!< RTCCTL0 Register */ +#define RTCCTL13 (HWREG16(0x40004402)) /*!< RTCCTL13 Register */ +#define RTCOCAL (HWREG16(0x40004404)) /*!< RTCOCAL Register */ +#define RTCTCMP (HWREG16(0x40004406)) /*!< RTCTCMP Register */ +#define RTCPS0CTL (HWREG16(0x40004408)) /*!< Real-Time Clock Prescale Timer 0 Control Register */ +#define RTCPS1CTL (HWREG16(0x4000440A)) /*!< Real-Time Clock Prescale Timer 1 Control Register */ +#define RTCPS (HWREG16(0x4000440C)) /*!< Real-Time Clock Prescale Timer Counter Register */ +#define RTCIV (HWREG16(0x4000440E)) /*!< Real-Time Clock Interrupt Vector Register */ +#define RTCTIM0 (HWREG16(0x40004410)) /*!< RTCTIM0 Register Hexadecimal Format */ +#define RTCTIM0_BCD (HWREG16(0x40004410)) +#define RTCTIM1 (HWREG16(0x40004412)) /*!< Real-Time Clock Hour, Day of Week */ +#define RTCTIM1_BCD (HWREG16(0x40004412)) +#define RTCDATE (HWREG16(0x40004414)) /*!< RTCDATE - Hexadecimal Format */ +#define RTCDATE_BCD (HWREG16(0x40004414)) +#define RTCYEAR (HWREG16(0x40004416)) /*!< RTCYEAR Register Hexadecimal Format */ +#define RTCYEAR_BCD (HWREG16(0x40004416)) +#define RTCAMINHR (HWREG16(0x40004418)) /*!< RTCMINHR - Hexadecimal Format */ +#define RTCAMINHR_BCD (HWREG16(0x40004418)) +#define RTCADOWDAY (HWREG16(0x4000441A)) /*!< RTCADOWDAY - Hexadecimal Format */ +#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) +#define RTCBIN2BCD (HWREG16(0x4000441C)) /*!< Binary-to-BCD Conversion Register */ +#define RTCBCD2BIN (HWREG16(0x4000441E)) /*!< BCD-to-Binary Conversion Register */ + +/* Register offsets from RTC_C_BASE address */ +#define OFS_RTCCTL0 (0x0000) /*!< RTCCTL0 Register */ +#define OFS_RTCCTL13 (0x0002) /*!< RTCCTL13 Register */ +#define OFS_RTCOCAL (0x0004) /*!< RTCOCAL Register */ +#define OFS_RTCTCMP (0x0006) /*!< RTCTCMP Register */ +#define OFS_RTCPS0CTL (0x0008) /*!< Real-Time Clock Prescale Timer 0 Control Register */ +#define OFS_RTCPS1CTL (0x000A) /*!< Real-Time Clock Prescale Timer 1 Control Register */ +#define OFS_RTCPS (0x000C) /*!< Real-Time Clock Prescale Timer Counter Register */ +#define OFS_RTCIV (0x000E) /*!< Real-Time Clock Interrupt Vector Register */ +#define OFS_RTCTIM0 (0x0010) /*!< RTCTIM0 Register Hexadecimal Format */ +#define OFS_RTCTIM0_BCD (0x0010) +#define OFS_RTCTIM1 (0x0012) /*!< Real-Time Clock Hour, Day of Week */ +#define OFS_RTCTIM1_BCD (0x0012) +#define OFS_RTCDATE (0x0014) /*!< RTCDATE - Hexadecimal Format */ +#define OFS_RTCDATE_BCD (0x0014) +#define OFS_RTCYEAR (0x0016) /*!< RTCYEAR Register Hexadecimal Format */ +#define OFS_RTCYEAR_BCD (0x0016) +#define OFS_RTCAMINHR (0x0018) /*!< RTCMINHR - Hexadecimal Format */ +#define OFS_RTCAMINHR_BCD (0x0018) +#define OFS_RTCADOWDAY (0x001A) /*!< RTCADOWDAY - Hexadecimal Format */ +#define OFS_RTCADOWDAY_BCD (0x001A) +#define OFS_RTCBIN2BCD (0x001C) /*!< Binary-to-BCD Conversion Register */ +#define OFS_RTCBCD2BIN (0x001E) /*!< BCD-to-Binary Conversion Register */ + +#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */ +#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */ +#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ +#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ +#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ +#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ +#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */ +#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */ +#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */ +#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */ +#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ +#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ +#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ +#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ +#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ +#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ +#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ +#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ +#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ +#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ +#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ +#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ +#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ +#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ +#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ +#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ +#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ +#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ +#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ +#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ +#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ +#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ +#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ +#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ +#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ +#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ +#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ +#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ + +/****************************************************************************** +* TIMER_A0 Registers +******************************************************************************/ +#define TA0CTL (HWREG16(0x40000000)) /*!< TimerAx Control Register */ +#define TA0CCTL0 (HWREG16(0x40000002)) /*!< Timer_A Capture/Compare Control Register */ +#define TA0CCTL1 (HWREG16(0x40000004)) /*!< Timer_A Capture/Compare Control Register */ +#define TA0CCTL2 (HWREG16(0x40000006)) /*!< Timer_A Capture/Compare Control Register */ +#define TA0CCTL3 (HWREG16(0x40000008)) /*!< Timer_A Capture/Compare Control Register */ +#define TA0CCTL4 (HWREG16(0x4000000A)) /*!< Timer_A Capture/Compare Control Register */ +#define TA0R (HWREG16(0x40000010)) /*!< TimerA register */ +#define TA0CCR0 (HWREG16(0x40000012)) /*!< Timer_A Capture/Compare Register */ +#define TA0CCR1 (HWREG16(0x40000014)) /*!< Timer_A Capture/Compare Register */ +#define TA0CCR2 (HWREG16(0x40000016)) /*!< Timer_A Capture/Compare Register */ +#define TA0CCR3 (HWREG16(0x40000018)) /*!< Timer_A Capture/Compare Register */ +#define TA0CCR4 (HWREG16(0x4000001A)) /*!< Timer_A Capture/Compare Register */ +#define TA0EX0 (HWREG16(0x40000020)) /*!< TimerAx Expansion 0 Register */ +#define TA0IV (HWREG16(0x4000002E)) /*!< TimerAx Interrupt Vector Register */ + +/* Register offsets from TIMER_A0_BASE address */ +#define OFS_TA0CTL (0x0000) /*!< TimerAx Control Register */ +#define OFS_TA0CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA0CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA0CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA0CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA0CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA0R (0x0010) /*!< TimerA register */ +#define OFS_TA0CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA0CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA0CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA0CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA0CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA0EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ +#define OFS_TA0IV (0x002E) /*!< TimerAx Interrupt Vector Register */ + + +/****************************************************************************** +* TIMER_A1 Registers +******************************************************************************/ +#define TA1CTL (HWREG16(0x40000400)) /*!< TimerAx Control Register */ +#define TA1CCTL0 (HWREG16(0x40000402)) /*!< Timer_A Capture/Compare Control Register */ +#define TA1CCTL1 (HWREG16(0x40000404)) /*!< Timer_A Capture/Compare Control Register */ +#define TA1CCTL2 (HWREG16(0x40000406)) /*!< Timer_A Capture/Compare Control Register */ +#define TA1CCTL3 (HWREG16(0x40000408)) /*!< Timer_A Capture/Compare Control Register */ +#define TA1CCTL4 (HWREG16(0x4000040A)) /*!< Timer_A Capture/Compare Control Register */ +#define TA1R (HWREG16(0x40000410)) /*!< TimerA register */ +#define TA1CCR0 (HWREG16(0x40000412)) /*!< Timer_A Capture/Compare Register */ +#define TA1CCR1 (HWREG16(0x40000414)) /*!< Timer_A Capture/Compare Register */ +#define TA1CCR2 (HWREG16(0x40000416)) /*!< Timer_A Capture/Compare Register */ +#define TA1CCR3 (HWREG16(0x40000418)) /*!< Timer_A Capture/Compare Register */ +#define TA1CCR4 (HWREG16(0x4000041A)) /*!< Timer_A Capture/Compare Register */ +#define TA1EX0 (HWREG16(0x40000420)) /*!< TimerAx Expansion 0 Register */ +#define TA1IV (HWREG16(0x4000042E)) /*!< TimerAx Interrupt Vector Register */ + +/* Register offsets from TIMER_A1_BASE address */ +#define OFS_TA1CTL (0x0000) /*!< TimerAx Control Register */ +#define OFS_TA1CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA1CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA1CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA1CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA1CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA1R (0x0010) /*!< TimerA register */ +#define OFS_TA1CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA1CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA1CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA1CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA1CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA1EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ +#define OFS_TA1IV (0x002E) /*!< TimerAx Interrupt Vector Register */ + + +/****************************************************************************** +* TIMER_A2 Registers +******************************************************************************/ +#define TA2CTL (HWREG16(0x40000800)) /*!< TimerAx Control Register */ +#define TA2CCTL0 (HWREG16(0x40000802)) /*!< Timer_A Capture/Compare Control Register */ +#define TA2CCTL1 (HWREG16(0x40000804)) /*!< Timer_A Capture/Compare Control Register */ +#define TA2CCTL2 (HWREG16(0x40000806)) /*!< Timer_A Capture/Compare Control Register */ +#define TA2CCTL3 (HWREG16(0x40000808)) /*!< Timer_A Capture/Compare Control Register */ +#define TA2CCTL4 (HWREG16(0x4000080A)) /*!< Timer_A Capture/Compare Control Register */ +#define TA2R (HWREG16(0x40000810)) /*!< TimerA register */ +#define TA2CCR0 (HWREG16(0x40000812)) /*!< Timer_A Capture/Compare Register */ +#define TA2CCR1 (HWREG16(0x40000814)) /*!< Timer_A Capture/Compare Register */ +#define TA2CCR2 (HWREG16(0x40000816)) /*!< Timer_A Capture/Compare Register */ +#define TA2CCR3 (HWREG16(0x40000818)) /*!< Timer_A Capture/Compare Register */ +#define TA2CCR4 (HWREG16(0x4000081A)) /*!< Timer_A Capture/Compare Register */ +#define TA2EX0 (HWREG16(0x40000820)) /*!< TimerAx Expansion 0 Register */ +#define TA2IV (HWREG16(0x4000082E)) /*!< TimerAx Interrupt Vector Register */ + +/* Register offsets from TIMER_A2_BASE address */ +#define OFS_TA2CTL (0x0000) /*!< TimerAx Control Register */ +#define OFS_TA2CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA2CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA2CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA2CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA2CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA2R (0x0010) /*!< TimerA register */ +#define OFS_TA2CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA2CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA2CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA2CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA2CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA2EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ +#define OFS_TA2IV (0x002E) /*!< TimerAx Interrupt Vector Register */ + + +/****************************************************************************** +* TIMER_A3 Registers +******************************************************************************/ +#define TA3CTL (HWREG16(0x40000C00)) /*!< TimerAx Control Register */ +#define TA3CCTL0 (HWREG16(0x40000C02)) /*!< Timer_A Capture/Compare Control Register */ +#define TA3CCTL1 (HWREG16(0x40000C04)) /*!< Timer_A Capture/Compare Control Register */ +#define TA3CCTL2 (HWREG16(0x40000C06)) /*!< Timer_A Capture/Compare Control Register */ +#define TA3CCTL3 (HWREG16(0x40000C08)) /*!< Timer_A Capture/Compare Control Register */ +#define TA3CCTL4 (HWREG16(0x40000C0A)) /*!< Timer_A Capture/Compare Control Register */ +#define TA3R (HWREG16(0x40000C10)) /*!< TimerA register */ +#define TA3CCR0 (HWREG16(0x40000C12)) /*!< Timer_A Capture/Compare Register */ +#define TA3CCR1 (HWREG16(0x40000C14)) /*!< Timer_A Capture/Compare Register */ +#define TA3CCR2 (HWREG16(0x40000C16)) /*!< Timer_A Capture/Compare Register */ +#define TA3CCR3 (HWREG16(0x40000C18)) /*!< Timer_A Capture/Compare Register */ +#define TA3CCR4 (HWREG16(0x40000C1A)) /*!< Timer_A Capture/Compare Register */ +#define TA3EX0 (HWREG16(0x40000C20)) /*!< TimerAx Expansion 0 Register */ +#define TA3IV (HWREG16(0x40000C2E)) /*!< TimerAx Interrupt Vector Register */ + +/* Register offsets from TIMER_A3_BASE address */ +#define OFS_TA3CTL (0x0000) /*!< TimerAx Control Register */ +#define OFS_TA3CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA3CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA3CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA3CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA3CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ +#define OFS_TA3R (0x0010) /*!< TimerA register */ +#define OFS_TA3CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA3CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA3CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA3CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA3CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ +#define OFS_TA3EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ +#define OFS_TA3IV (0x002E) /*!< TimerAx Interrupt Vector Register */ + + +/****************************************************************************** +* WDT_A Registers +******************************************************************************/ +#define WDTCTL (HWREG16(0x4000480C)) /*!< Watchdog Timer Control Register */ + +/* Register offsets from WDT_A_BASE address */ +#define OFS_WDTCTL (0x000C) /*!< Watchdog Timer Control Register */ + + +/****************************************************************************** +* Peripheral register control bits (legacy section) * +******************************************************************************/ + +/****************************************************************************** +* AES256 Bits (legacy section) +******************************************************************************/ +/* AESACTL0[AESOP] Bits */ +#define AESOP_OFS AES256_CTL0_OP_OFS /*!< AESOP Offset */ +#define AESOP_M AES256_CTL0_OP_MASK /*!< AES operation */ +#define AESOP0 AES256_CTL0_OP0 /*!< AESOP Bit 0 */ +#define AESOP1 AES256_CTL0_OP1 /*!< AESOP Bit 1 */ +#define AESOP_0 AES256_CTL0_OP_0 /*!< Encryption */ +#define AESOP_1 AES256_CTL0_OP_1 /*!< Decryption. The provided key is the same key used for encryption */ +#define AESOP_2 AES256_CTL0_OP_2 /*!< Generate first round key required for decryption */ +#define AESOP_3 AES256_CTL0_OP_3 /*!< Decryption. The provided key is the first round key required for decryption */ +/* AESACTL0[AESKL] Bits */ +#define AESKL_OFS AES256_CTL0_KL_OFS /*!< AESKL Offset */ +#define AESKL_M AES256_CTL0_KL_MASK /*!< AES key length */ +#define AESKL0 AES256_CTL0_KL0 /*!< AESKL Bit 0 */ +#define AESKL1 AES256_CTL0_KL1 /*!< AESKL Bit 1 */ +#define AESKL_0 AES256_CTL0_KL_0 /*!< AES128. The key size is 128 bit */ +#define AESKL_1 AES256_CTL0_KL_1 /*!< AES192. The key size is 192 bit. */ +#define AESKL_2 AES256_CTL0_KL_2 /*!< AES256. The key size is 256 bit */ +#define AESKL__128BIT AES256_CTL0_KL__128BIT /*!< AES128. The key size is 128 bit */ +#define AESKL__192BIT AES256_CTL0_KL__192BIT /*!< AES192. The key size is 192 bit. */ +#define AESKL__256BIT AES256_CTL0_KL__256BIT /*!< AES256. The key size is 256 bit */ +/* AESACTL0[AESCM] Bits */ +#define AESCM_OFS AES256_CTL0_CM_OFS /*!< AESCM Offset */ +#define AESCM_M AES256_CTL0_CM_MASK /*!< AES cipher mode select */ +#define AESCM0 AES256_CTL0_CM0 /*!< AESCM Bit 0 */ +#define AESCM1 AES256_CTL0_CM1 /*!< AESCM Bit 1 */ +#define AESCM_0 AES256_CTL0_CM_0 /*!< ECB */ +#define AESCM_1 AES256_CTL0_CM_1 /*!< CBC */ +#define AESCM_2 AES256_CTL0_CM_2 /*!< OFB */ +#define AESCM_3 AES256_CTL0_CM_3 /*!< CFB */ +#define AESCM__ECB AES256_CTL0_CM__ECB /*!< ECB */ +#define AESCM__CBC AES256_CTL0_CM__CBC /*!< CBC */ +#define AESCM__OFB AES256_CTL0_CM__OFB /*!< OFB */ +#define AESCM__CFB AES256_CTL0_CM__CFB /*!< CFB */ +/* AESACTL0[AESSWRST] Bits */ +#define AESSWRST_OFS AES256_CTL0_SWRST_OFS /*!< AESSWRST Offset */ +#define AESSWRST AES256_CTL0_SWRST /*!< AES software reset */ +/* AESACTL0[AESRDYIFG] Bits */ +#define AESRDYIFG_OFS AES256_CTL0_RDYIFG_OFS /*!< AESRDYIFG Offset */ +#define AESRDYIFG AES256_CTL0_RDYIFG /*!< AES ready interrupt flag */ +/* AESACTL0[AESERRFG] Bits */ +#define AESERRFG_OFS AES256_CTL0_ERRFG_OFS /*!< AESERRFG Offset */ +#define AESERRFG AES256_CTL0_ERRFG /*!< AES error flag */ +/* AESACTL0[AESRDYIE] Bits */ +#define AESRDYIE_OFS AES256_CTL0_RDYIE_OFS /*!< AESRDYIE Offset */ +#define AESRDYIE AES256_CTL0_RDYIE /*!< AES ready interrupt enable */ +/* AESACTL0[AESCMEN] Bits */ +#define AESCMEN_OFS AES256_CTL0_CMEN_OFS /*!< AESCMEN Offset */ +#define AESCMEN AES256_CTL0_CMEN /*!< AES cipher mode enable */ +/* AESACTL1[AESBLKCNT] Bits */ +#define AESBLKCNT_OFS AES256_CTL1_BLKCNT_OFS /*!< AESBLKCNT Offset */ +#define AESBLKCNT_M AES256_CTL1_BLKCNT_MASK /*!< Cipher Block Counter */ +#define AESBLKCNT0 AES256_CTL1_BLKCNT0 /*!< AESBLKCNT Bit 0 */ +#define AESBLKCNT1 AES256_CTL1_BLKCNT1 /*!< AESBLKCNT Bit 1 */ +#define AESBLKCNT2 AES256_CTL1_BLKCNT2 /*!< AESBLKCNT Bit 2 */ +#define AESBLKCNT3 AES256_CTL1_BLKCNT3 /*!< AESBLKCNT Bit 3 */ +#define AESBLKCNT4 AES256_CTL1_BLKCNT4 /*!< AESBLKCNT Bit 4 */ +#define AESBLKCNT5 AES256_CTL1_BLKCNT5 /*!< AESBLKCNT Bit 5 */ +#define AESBLKCNT6 AES256_CTL1_BLKCNT6 /*!< AESBLKCNT Bit 6 */ +#define AESBLKCNT7 AES256_CTL1_BLKCNT7 /*!< AESBLKCNT Bit 7 */ +/* AESASTAT[AESBUSY] Bits */ +#define AESBUSY_OFS AES256_STAT_BUSY_OFS /*!< AESBUSY Offset */ +#define AESBUSY AES256_STAT_BUSY /*!< AES accelerator module busy */ +/* AESASTAT[AESKEYWR] Bits */ +#define AESKEYWR_OFS AES256_STAT_KEYWR_OFS /*!< AESKEYWR Offset */ +#define AESKEYWR AES256_STAT_KEYWR /*!< All 16 bytes written to AESAKEY */ +/* AESASTAT[AESDINWR] Bits */ +#define AESDINWR_OFS AES256_STAT_DINWR_OFS /*!< AESDINWR Offset */ +#define AESDINWR AES256_STAT_DINWR /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ +/* AESASTAT[AESDOUTRD] Bits */ +#define AESDOUTRD_OFS AES256_STAT_DOUTRD_OFS /*!< AESDOUTRD Offset */ +#define AESDOUTRD AES256_STAT_DOUTRD /*!< All 16 bytes read from AESADOUT */ +/* AESASTAT[AESKEYCNT] Bits */ +#define AESKEYCNT_OFS AES256_STAT_KEYCNT_OFS /*!< AESKEYCNT Offset */ +#define AESKEYCNT_M AES256_STAT_KEYCNT_MASK /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */ +#define AESKEYCNT0 AES256_STAT_KEYCNT0 /*!< AESKEYCNT Bit 0 */ +#define AESKEYCNT1 AES256_STAT_KEYCNT1 /*!< AESKEYCNT Bit 1 */ +#define AESKEYCNT2 AES256_STAT_KEYCNT2 /*!< AESKEYCNT Bit 2 */ +#define AESKEYCNT3 AES256_STAT_KEYCNT3 /*!< AESKEYCNT Bit 3 */ +/* AESASTAT[AESDINCNT] Bits */ +#define AESDINCNT_OFS AES256_STAT_DINCNT_OFS /*!< AESDINCNT Offset */ +#define AESDINCNT_M AES256_STAT_DINCNT_MASK /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */ +#define AESDINCNT0 AES256_STAT_DINCNT0 /*!< AESDINCNT Bit 0 */ +#define AESDINCNT1 AES256_STAT_DINCNT1 /*!< AESDINCNT Bit 1 */ +#define AESDINCNT2 AES256_STAT_DINCNT2 /*!< AESDINCNT Bit 2 */ +#define AESDINCNT3 AES256_STAT_DINCNT3 /*!< AESDINCNT Bit 3 */ +/* AESASTAT[AESDOUTCNT] Bits */ +#define AESDOUTCNT_OFS AES256_STAT_DOUTCNT_OFS /*!< AESDOUTCNT Offset */ +#define AESDOUTCNT_M AES256_STAT_DOUTCNT_MASK /*!< Bytes read via AESADOUT */ +#define AESDOUTCNT0 AES256_STAT_DOUTCNT0 /*!< AESDOUTCNT Bit 0 */ +#define AESDOUTCNT1 AES256_STAT_DOUTCNT1 /*!< AESDOUTCNT Bit 1 */ +#define AESDOUTCNT2 AES256_STAT_DOUTCNT2 /*!< AESDOUTCNT Bit 2 */ +#define AESDOUTCNT3 AES256_STAT_DOUTCNT3 /*!< AESDOUTCNT Bit 3 */ +/* AESAKEY[AESKEY0] Bits */ +#define AESKEY0_OFS AES256_KEY_KEY0_OFS /*!< AESKEY0 Offset */ +#define AESKEY0_M AES256_KEY_KEY0_MASK /*!< AES key byte n when AESAKEY is written as half-word */ +#define AESKEY00 AES256_KEY_KEY00 /*!< AESKEY0 Bit 0 */ +#define AESKEY01 AES256_KEY_KEY01 /*!< AESKEY0 Bit 1 */ +#define AESKEY02 AES256_KEY_KEY02 /*!< AESKEY0 Bit 2 */ +#define AESKEY03 AES256_KEY_KEY03 /*!< AESKEY0 Bit 3 */ +#define AESKEY04 AES256_KEY_KEY04 /*!< AESKEY0 Bit 4 */ +#define AESKEY05 AES256_KEY_KEY05 /*!< AESKEY0 Bit 5 */ +#define AESKEY06 AES256_KEY_KEY06 /*!< AESKEY0 Bit 6 */ +#define AESKEY07 AES256_KEY_KEY07 /*!< AESKEY0 Bit 7 */ +/* AESAKEY[AESKEY1] Bits */ +#define AESKEY1_OFS AES256_KEY_KEY1_OFS /*!< AESKEY1 Offset */ +#define AESKEY1_M AES256_KEY_KEY1_MASK /*!< AES key byte n+1 when AESAKEY is written as half-word */ +#define AESKEY10 AES256_KEY_KEY10 /*!< AESKEY1 Bit 0 */ +#define AESKEY11 AES256_KEY_KEY11 /*!< AESKEY1 Bit 1 */ +#define AESKEY12 AES256_KEY_KEY12 /*!< AESKEY1 Bit 2 */ +#define AESKEY13 AES256_KEY_KEY13 /*!< AESKEY1 Bit 3 */ +#define AESKEY14 AES256_KEY_KEY14 /*!< AESKEY1 Bit 4 */ +#define AESKEY15 AES256_KEY_KEY15 /*!< AESKEY1 Bit 5 */ +#define AESKEY16 AES256_KEY_KEY16 /*!< AESKEY1 Bit 6 */ +#define AESKEY17 AES256_KEY_KEY17 /*!< AESKEY1 Bit 7 */ +/* AESADIN[AESDIN0] Bits */ +#define AESDIN0_OFS AES256_DIN_DIN0_OFS /*!< AESDIN0 Offset */ +#define AESDIN0_M AES256_DIN_DIN0_MASK /*!< AES data in byte n when AESADIN is written as half-word */ +#define AESDIN00 AES256_DIN_DIN00 /*!< AESDIN0 Bit 0 */ +#define AESDIN01 AES256_DIN_DIN01 /*!< AESDIN0 Bit 1 */ +#define AESDIN02 AES256_DIN_DIN02 /*!< AESDIN0 Bit 2 */ +#define AESDIN03 AES256_DIN_DIN03 /*!< AESDIN0 Bit 3 */ +#define AESDIN04 AES256_DIN_DIN04 /*!< AESDIN0 Bit 4 */ +#define AESDIN05 AES256_DIN_DIN05 /*!< AESDIN0 Bit 5 */ +#define AESDIN06 AES256_DIN_DIN06 /*!< AESDIN0 Bit 6 */ +#define AESDIN07 AES256_DIN_DIN07 /*!< AESDIN0 Bit 7 */ +/* AESADIN[AESDIN1] Bits */ +#define AESDIN1_OFS AES256_DIN_DIN1_OFS /*!< AESDIN1 Offset */ +#define AESDIN1_M AES256_DIN_DIN1_MASK /*!< AES data in byte n+1 when AESADIN is written as half-word */ +#define AESDIN10 AES256_DIN_DIN10 /*!< AESDIN1 Bit 0 */ +#define AESDIN11 AES256_DIN_DIN11 /*!< AESDIN1 Bit 1 */ +#define AESDIN12 AES256_DIN_DIN12 /*!< AESDIN1 Bit 2 */ +#define AESDIN13 AES256_DIN_DIN13 /*!< AESDIN1 Bit 3 */ +#define AESDIN14 AES256_DIN_DIN14 /*!< AESDIN1 Bit 4 */ +#define AESDIN15 AES256_DIN_DIN15 /*!< AESDIN1 Bit 5 */ +#define AESDIN16 AES256_DIN_DIN16 /*!< AESDIN1 Bit 6 */ +#define AESDIN17 AES256_DIN_DIN17 /*!< AESDIN1 Bit 7 */ +/* AESADOUT[AESDOUT0] Bits */ +#define AESDOUT0_OFS AES256_DOUT_DOUT0_OFS /*!< AESDOUT0 Offset */ +#define AESDOUT0_M AES256_DOUT_DOUT0_MASK /*!< AES data out byte n when AESADOUT is read as half-word */ +#define AESDOUT00 AES256_DOUT_DOUT00 /*!< AESDOUT0 Bit 0 */ +#define AESDOUT01 AES256_DOUT_DOUT01 /*!< AESDOUT0 Bit 1 */ +#define AESDOUT02 AES256_DOUT_DOUT02 /*!< AESDOUT0 Bit 2 */ +#define AESDOUT03 AES256_DOUT_DOUT03 /*!< AESDOUT0 Bit 3 */ +#define AESDOUT04 AES256_DOUT_DOUT04 /*!< AESDOUT0 Bit 4 */ +#define AESDOUT05 AES256_DOUT_DOUT05 /*!< AESDOUT0 Bit 5 */ +#define AESDOUT06 AES256_DOUT_DOUT06 /*!< AESDOUT0 Bit 6 */ +#define AESDOUT07 AES256_DOUT_DOUT07 /*!< AESDOUT0 Bit 7 */ +/* AESADOUT[AESDOUT1] Bits */ +#define AESDOUT1_OFS AES256_DOUT_DOUT1_OFS /*!< AESDOUT1 Offset */ +#define AESDOUT1_M AES256_DOUT_DOUT1_MASK /*!< AES data out byte n+1 when AESADOUT is read as half-word */ +#define AESDOUT10 AES256_DOUT_DOUT10 /*!< AESDOUT1 Bit 0 */ +#define AESDOUT11 AES256_DOUT_DOUT11 /*!< AESDOUT1 Bit 1 */ +#define AESDOUT12 AES256_DOUT_DOUT12 /*!< AESDOUT1 Bit 2 */ +#define AESDOUT13 AES256_DOUT_DOUT13 /*!< AESDOUT1 Bit 3 */ +#define AESDOUT14 AES256_DOUT_DOUT14 /*!< AESDOUT1 Bit 4 */ +#define AESDOUT15 AES256_DOUT_DOUT15 /*!< AESDOUT1 Bit 5 */ +#define AESDOUT16 AES256_DOUT_DOUT16 /*!< AESDOUT1 Bit 6 */ +#define AESDOUT17 AES256_DOUT_DOUT17 /*!< AESDOUT1 Bit 7 */ +/* AESAXDIN[AESXDIN0] Bits */ +#define AESXDIN0_OFS AES256_XDIN_XDIN0_OFS /*!< AESXDIN0 Offset */ +#define AESXDIN0_M AES256_XDIN_XDIN0_MASK /*!< AES data in byte n when AESAXDIN is written as half-word */ +#define AESXDIN00 AES256_XDIN_XDIN00 /*!< AESXDIN0 Bit 0 */ +#define AESXDIN01 AES256_XDIN_XDIN01 /*!< AESXDIN0 Bit 1 */ +#define AESXDIN02 AES256_XDIN_XDIN02 /*!< AESXDIN0 Bit 2 */ +#define AESXDIN03 AES256_XDIN_XDIN03 /*!< AESXDIN0 Bit 3 */ +#define AESXDIN04 AES256_XDIN_XDIN04 /*!< AESXDIN0 Bit 4 */ +#define AESXDIN05 AES256_XDIN_XDIN05 /*!< AESXDIN0 Bit 5 */ +#define AESXDIN06 AES256_XDIN_XDIN06 /*!< AESXDIN0 Bit 6 */ +#define AESXDIN07 AES256_XDIN_XDIN07 /*!< AESXDIN0 Bit 7 */ +/* AESAXDIN[AESXDIN1] Bits */ +#define AESXDIN1_OFS AES256_XDIN_XDIN1_OFS /*!< AESXDIN1 Offset */ +#define AESXDIN1_M AES256_XDIN_XDIN1_MASK /*!< AES data in byte n+1 when AESAXDIN is written as half-word */ +#define AESXDIN10 AES256_XDIN_XDIN10 /*!< AESXDIN1 Bit 0 */ +#define AESXDIN11 AES256_XDIN_XDIN11 /*!< AESXDIN1 Bit 1 */ +#define AESXDIN12 AES256_XDIN_XDIN12 /*!< AESXDIN1 Bit 2 */ +#define AESXDIN13 AES256_XDIN_XDIN13 /*!< AESXDIN1 Bit 3 */ +#define AESXDIN14 AES256_XDIN_XDIN14 /*!< AESXDIN1 Bit 4 */ +#define AESXDIN15 AES256_XDIN_XDIN15 /*!< AESXDIN1 Bit 5 */ +#define AESXDIN16 AES256_XDIN_XDIN16 /*!< AESXDIN1 Bit 6 */ +#define AESXDIN17 AES256_XDIN_XDIN17 /*!< AESXDIN1 Bit 7 */ +/* AESAXIN[AESXIN0] Bits */ +#define AESXIN0_OFS AES256_XIN_XIN0_OFS /*!< AESXIN0 Offset */ +#define AESXIN0_M AES256_XIN_XIN0_MASK /*!< AES data in byte n when AESAXIN is written as half-word */ +#define AESXIN00 AES256_XIN_XIN00 /*!< AESXIN0 Bit 0 */ +#define AESXIN01 AES256_XIN_XIN01 /*!< AESXIN0 Bit 1 */ +#define AESXIN02 AES256_XIN_XIN02 /*!< AESXIN0 Bit 2 */ +#define AESXIN03 AES256_XIN_XIN03 /*!< AESXIN0 Bit 3 */ +#define AESXIN04 AES256_XIN_XIN04 /*!< AESXIN0 Bit 4 */ +#define AESXIN05 AES256_XIN_XIN05 /*!< AESXIN0 Bit 5 */ +#define AESXIN06 AES256_XIN_XIN06 /*!< AESXIN0 Bit 6 */ +#define AESXIN07 AES256_XIN_XIN07 /*!< AESXIN0 Bit 7 */ +/* AESAXIN[AESXIN1] Bits */ +#define AESXIN1_OFS AES256_XIN_XIN1_OFS /*!< AESXIN1 Offset */ +#define AESXIN1_M AES256_XIN_XIN1_MASK /*!< AES data in byte n+1 when AESAXIN is written as half-word */ +#define AESXIN10 AES256_XIN_XIN10 /*!< AESXIN1 Bit 0 */ +#define AESXIN11 AES256_XIN_XIN11 /*!< AESXIN1 Bit 1 */ +#define AESXIN12 AES256_XIN_XIN12 /*!< AESXIN1 Bit 2 */ +#define AESXIN13 AES256_XIN_XIN13 /*!< AESXIN1 Bit 3 */ +#define AESXIN14 AES256_XIN_XIN14 /*!< AESXIN1 Bit 4 */ +#define AESXIN15 AES256_XIN_XIN15 /*!< AESXIN1 Bit 5 */ +#define AESXIN16 AES256_XIN_XIN16 /*!< AESXIN1 Bit 6 */ +#define AESXIN17 AES256_XIN_XIN17 /*!< AESXIN1 Bit 7 */ + +/****************************************************************************** +* CAPTIO Bits (legacy section) +******************************************************************************/ +/* CAPTIO0CTL[CAPTIOPISEL] Bits */ +#define CAPTIOPISEL_OFS CAPTIO_CTL_PISEL_OFS /*!< CAPTIOPISEL Offset */ +#define CAPTIOPISEL_M CAPTIO_CTL_PISEL_MASK /*!< Capacitive Touch IO pin select */ +#define CAPTIOPISEL0 CAPTIO_CTL_PISEL0 /*!< CAPTIOPISEL Bit 0 */ +#define CAPTIOPISEL1 CAPTIO_CTL_PISEL1 /*!< CAPTIOPISEL Bit 1 */ +#define CAPTIOPISEL2 CAPTIO_CTL_PISEL2 /*!< CAPTIOPISEL Bit 2 */ +#define CAPTIOPISEL_0 CAPTIO_CTL_PISEL_0 /*!< Px.0 */ +#define CAPTIOPISEL_1 CAPTIO_CTL_PISEL_1 /*!< Px.1 */ +#define CAPTIOPISEL_2 CAPTIO_CTL_PISEL_2 /*!< Px.2 */ +#define CAPTIOPISEL_3 CAPTIO_CTL_PISEL_3 /*!< Px.3 */ +#define CAPTIOPISEL_4 CAPTIO_CTL_PISEL_4 /*!< Px.4 */ +#define CAPTIOPISEL_5 CAPTIO_CTL_PISEL_5 /*!< Px.5 */ +#define CAPTIOPISEL_6 CAPTIO_CTL_PISEL_6 /*!< Px.6 */ +#define CAPTIOPISEL_7 CAPTIO_CTL_PISEL_7 /*!< Px.7 */ +/* CAPTIO0CTL[CAPTIOPOSEL] Bits */ +#define CAPTIOPOSEL_OFS CAPTIO_CTL_POSEL_OFS /*!< CAPTIOPOSEL Offset */ +#define CAPTIOPOSEL_M CAPTIO_CTL_POSEL_MASK /*!< Capacitive Touch IO port select */ +#define CAPTIOPOSEL0 CAPTIO_CTL_POSEL0 /*!< CAPTIOPOSEL Bit 0 */ +#define CAPTIOPOSEL1 CAPTIO_CTL_POSEL1 /*!< CAPTIOPOSEL Bit 1 */ +#define CAPTIOPOSEL2 CAPTIO_CTL_POSEL2 /*!< CAPTIOPOSEL Bit 2 */ +#define CAPTIOPOSEL3 CAPTIO_CTL_POSEL3 /*!< CAPTIOPOSEL Bit 3 */ +#define CAPTIOPOSEL_0 CAPTIO_CTL_POSEL_0 /*!< Px = PJ */ +#define CAPTIOPOSEL_1 CAPTIO_CTL_POSEL_1 /*!< Px = P1 */ +#define CAPTIOPOSEL_2 CAPTIO_CTL_POSEL_2 /*!< Px = P2 */ +#define CAPTIOPOSEL_3 CAPTIO_CTL_POSEL_3 /*!< Px = P3 */ +#define CAPTIOPOSEL_4 CAPTIO_CTL_POSEL_4 /*!< Px = P4 */ +#define CAPTIOPOSEL_5 CAPTIO_CTL_POSEL_5 /*!< Px = P5 */ +#define CAPTIOPOSEL_6 CAPTIO_CTL_POSEL_6 /*!< Px = P6 */ +#define CAPTIOPOSEL_7 CAPTIO_CTL_POSEL_7 /*!< Px = P7 */ +#define CAPTIOPOSEL_8 CAPTIO_CTL_POSEL_8 /*!< Px = P8 */ +#define CAPTIOPOSEL_9 CAPTIO_CTL_POSEL_9 /*!< Px = P9 */ +#define CAPTIOPOSEL_10 CAPTIO_CTL_POSEL_10 /*!< Px = P10 */ +#define CAPTIOPOSEL_11 CAPTIO_CTL_POSEL_11 /*!< Px = P11 */ +#define CAPTIOPOSEL_12 CAPTIO_CTL_POSEL_12 /*!< Px = P12 */ +#define CAPTIOPOSEL_13 CAPTIO_CTL_POSEL_13 /*!< Px = P13 */ +#define CAPTIOPOSEL_14 CAPTIO_CTL_POSEL_14 /*!< Px = P14 */ +#define CAPTIOPOSEL_15 CAPTIO_CTL_POSEL_15 /*!< Px = P15 */ +#define CAPTIOPOSEL__PJ CAPTIO_CTL_POSEL__PJ /*!< Px = PJ */ +#define CAPTIOPOSEL__P1 CAPTIO_CTL_POSEL__P1 /*!< Px = P1 */ +#define CAPTIOPOSEL__P2 CAPTIO_CTL_POSEL__P2 /*!< Px = P2 */ +#define CAPTIOPOSEL__P3 CAPTIO_CTL_POSEL__P3 /*!< Px = P3 */ +#define CAPTIOPOSEL__P4 CAPTIO_CTL_POSEL__P4 /*!< Px = P4 */ +#define CAPTIOPOSEL__P5 CAPTIO_CTL_POSEL__P5 /*!< Px = P5 */ +#define CAPTIOPOSEL__P6 CAPTIO_CTL_POSEL__P6 /*!< Px = P6 */ +#define CAPTIOPOSEL__P7 CAPTIO_CTL_POSEL__P7 /*!< Px = P7 */ +#define CAPTIOPOSEL__P8 CAPTIO_CTL_POSEL__P8 /*!< Px = P8 */ +#define CAPTIOPOSEL__P9 CAPTIO_CTL_POSEL__P9 /*!< Px = P9 */ +#define CAPTIOPOSEL__P10 CAPTIO_CTL_POSEL__P10 /*!< Px = P10 */ +#define CAPTIOPOSEL__P11 CAPTIO_CTL_POSEL__P11 /*!< Px = P11 */ +#define CAPTIOPOSEL__P12 CAPTIO_CTL_POSEL__P12 /*!< Px = P12 */ +#define CAPTIOPOSEL__P13 CAPTIO_CTL_POSEL__P13 /*!< Px = P13 */ +#define CAPTIOPOSEL__P14 CAPTIO_CTL_POSEL__P14 /*!< Px = P14 */ +#define CAPTIOPOSEL__P15 CAPTIO_CTL_POSEL__P15 /*!< Px = P15 */ +/* CAPTIO0CTL[CAPTIOEN] Bits */ +#define CAPTIOEN_OFS CAPTIO_CTL_EN_OFS /*!< CAPTIOEN Offset */ +#define CAPTIOEN CAPTIO_CTL_EN /*!< Capacitive Touch IO enable */ +/* CAPTIO0CTL[CAPTIOSTATE] Bits */ +#define CAPTIOSTATE_OFS CAPTIO_CTL_STATE_OFS /*!< CAPTIOSTATE Offset */ +#define CAPTIOSTATE CAPTIO_CTL_STATE /*!< Capacitive Touch IO state */ + +/****************************************************************************** +* COMP_E Bits (legacy section) +******************************************************************************/ +/* CE0CTL0[CEIPSEL] Bits */ +#define CEIPSEL_OFS COMP_E_CTL0_IPSEL_OFS /*!< CEIPSEL Offset */ +#define CEIPSEL_M COMP_E_CTL0_IPSEL_MASK /*!< Channel input selected for the V+ terminal */ +#define CEIPSEL0 COMP_E_CTL0_IPSEL0 /*!< CEIPSEL Bit 0 */ +#define CEIPSEL1 COMP_E_CTL0_IPSEL1 /*!< CEIPSEL Bit 1 */ +#define CEIPSEL2 COMP_E_CTL0_IPSEL2 /*!< CEIPSEL Bit 2 */ +#define CEIPSEL3 COMP_E_CTL0_IPSEL3 /*!< CEIPSEL Bit 3 */ +#define CEIPSEL_0 COMP_E_CTL0_IPSEL_0 /*!< Channel 0 selected */ +#define CEIPSEL_1 COMP_E_CTL0_IPSEL_1 /*!< Channel 1 selected */ +#define CEIPSEL_2 COMP_E_CTL0_IPSEL_2 /*!< Channel 2 selected */ +#define CEIPSEL_3 COMP_E_CTL0_IPSEL_3 /*!< Channel 3 selected */ +#define CEIPSEL_4 COMP_E_CTL0_IPSEL_4 /*!< Channel 4 selected */ +#define CEIPSEL_5 COMP_E_CTL0_IPSEL_5 /*!< Channel 5 selected */ +#define CEIPSEL_6 COMP_E_CTL0_IPSEL_6 /*!< Channel 6 selected */ +#define CEIPSEL_7 COMP_E_CTL0_IPSEL_7 /*!< Channel 7 selected */ +#define CEIPSEL_8 COMP_E_CTL0_IPSEL_8 /*!< Channel 8 selected */ +#define CEIPSEL_9 COMP_E_CTL0_IPSEL_9 /*!< Channel 9 selected */ +#define CEIPSEL_10 COMP_E_CTL0_IPSEL_10 /*!< Channel 10 selected */ +#define CEIPSEL_11 COMP_E_CTL0_IPSEL_11 /*!< Channel 11 selected */ +#define CEIPSEL_12 COMP_E_CTL0_IPSEL_12 /*!< Channel 12 selected */ +#define CEIPSEL_13 COMP_E_CTL0_IPSEL_13 /*!< Channel 13 selected */ +#define CEIPSEL_14 COMP_E_CTL0_IPSEL_14 /*!< Channel 14 selected */ +#define CEIPSEL_15 COMP_E_CTL0_IPSEL_15 /*!< Channel 15 selected */ +/* CE0CTL0[CEIPEN] Bits */ +#define CEIPEN_OFS COMP_E_CTL0_IPEN_OFS /*!< CEIPEN Offset */ +#define CEIPEN COMP_E_CTL0_IPEN /*!< Channel input enable for the V+ terminal */ +/* CE0CTL0[CEIMSEL] Bits */ +#define CEIMSEL_OFS COMP_E_CTL0_IMSEL_OFS /*!< CEIMSEL Offset */ +#define CEIMSEL_M COMP_E_CTL0_IMSEL_MASK /*!< Channel input selected for the - terminal */ +#define CEIMSEL0 COMP_E_CTL0_IMSEL0 /*!< CEIMSEL Bit 0 */ +#define CEIMSEL1 COMP_E_CTL0_IMSEL1 /*!< CEIMSEL Bit 1 */ +#define CEIMSEL2 COMP_E_CTL0_IMSEL2 /*!< CEIMSEL Bit 2 */ +#define CEIMSEL3 COMP_E_CTL0_IMSEL3 /*!< CEIMSEL Bit 3 */ +#define CEIMSEL_0 COMP_E_CTL0_IMSEL_0 /*!< Channel 0 selected */ +#define CEIMSEL_1 COMP_E_CTL0_IMSEL_1 /*!< Channel 1 selected */ +#define CEIMSEL_2 COMP_E_CTL0_IMSEL_2 /*!< Channel 2 selected */ +#define CEIMSEL_3 COMP_E_CTL0_IMSEL_3 /*!< Channel 3 selected */ +#define CEIMSEL_4 COMP_E_CTL0_IMSEL_4 /*!< Channel 4 selected */ +#define CEIMSEL_5 COMP_E_CTL0_IMSEL_5 /*!< Channel 5 selected */ +#define CEIMSEL_6 COMP_E_CTL0_IMSEL_6 /*!< Channel 6 selected */ +#define CEIMSEL_7 COMP_E_CTL0_IMSEL_7 /*!< Channel 7 selected */ +#define CEIMSEL_8 COMP_E_CTL0_IMSEL_8 /*!< Channel 8 selected */ +#define CEIMSEL_9 COMP_E_CTL0_IMSEL_9 /*!< Channel 9 selected */ +#define CEIMSEL_10 COMP_E_CTL0_IMSEL_10 /*!< Channel 10 selected */ +#define CEIMSEL_11 COMP_E_CTL0_IMSEL_11 /*!< Channel 11 selected */ +#define CEIMSEL_12 COMP_E_CTL0_IMSEL_12 /*!< Channel 12 selected */ +#define CEIMSEL_13 COMP_E_CTL0_IMSEL_13 /*!< Channel 13 selected */ +#define CEIMSEL_14 COMP_E_CTL0_IMSEL_14 /*!< Channel 14 selected */ +#define CEIMSEL_15 COMP_E_CTL0_IMSEL_15 /*!< Channel 15 selected */ +/* CE0CTL0[CEIMEN] Bits */ +#define CEIMEN_OFS COMP_E_CTL0_IMEN_OFS /*!< CEIMEN Offset */ +#define CEIMEN COMP_E_CTL0_IMEN /*!< Channel input enable for the - terminal */ +/* CE0CTL1[CEOUT] Bits */ +#define CEOUT_OFS COMP_E_CTL1_OUT_OFS /*!< CEOUT Offset */ +#define CEOUT COMP_E_CTL1_OUT /*!< Comparator output value */ +/* CE0CTL1[CEOUTPOL] Bits */ +#define CEOUTPOL_OFS COMP_E_CTL1_OUTPOL_OFS /*!< CEOUTPOL Offset */ +#define CEOUTPOL COMP_E_CTL1_OUTPOL /*!< Comparator output polarity */ +/* CE0CTL1[CEF] Bits */ +#define CEF_OFS COMP_E_CTL1_F_OFS /*!< CEF Offset */ +#define CEF COMP_E_CTL1_F /*!< Comparator output filter */ +/* CE0CTL1[CEIES] Bits */ +#define CEIES_OFS COMP_E_CTL1_IES_OFS /*!< CEIES Offset */ +#define CEIES COMP_E_CTL1_IES /*!< Interrupt edge select for CEIIFG and CEIFG */ +/* CE0CTL1[CESHORT] Bits */ +#define CESHORT_OFS COMP_E_CTL1_SHORT_OFS /*!< CESHORT Offset */ +#define CESHORT COMP_E_CTL1_SHORT /*!< Input short */ +/* CE0CTL1[CEEX] Bits */ +#define CEEX_OFS COMP_E_CTL1_EX_OFS /*!< CEEX Offset */ +#define CEEX COMP_E_CTL1_EX /*!< Exchange */ +/* CE0CTL1[CEFDLY] Bits */ +#define CEFDLY_OFS COMP_E_CTL1_FDLY_OFS /*!< CEFDLY Offset */ +#define CEFDLY_M COMP_E_CTL1_FDLY_MASK /*!< Filter delay */ +#define CEFDLY0 COMP_E_CTL1_FDLY0 /*!< CEFDLY Bit 0 */ +#define CEFDLY1 COMP_E_CTL1_FDLY1 /*!< CEFDLY Bit 1 */ +#define CEFDLY_0 COMP_E_CTL1_FDLY_0 /*!< Typical filter delay of TBD (450) ns */ +#define CEFDLY_1 COMP_E_CTL1_FDLY_1 /*!< Typical filter delay of TBD (900) ns */ +#define CEFDLY_2 COMP_E_CTL1_FDLY_2 /*!< Typical filter delay of TBD (1800) ns */ +#define CEFDLY_3 COMP_E_CTL1_FDLY_3 /*!< Typical filter delay of TBD (3600) ns */ +/* CE0CTL1[CEPWRMD] Bits */ +#define CEPWRMD_OFS COMP_E_CTL1_PWRMD_OFS /*!< CEPWRMD Offset */ +#define CEPWRMD_M COMP_E_CTL1_PWRMD_MASK /*!< Power Mode */ +#define CEPWRMD0 COMP_E_CTL1_PWRMD0 /*!< CEPWRMD Bit 0 */ +#define CEPWRMD1 COMP_E_CTL1_PWRMD1 /*!< CEPWRMD Bit 1 */ +#define CEPWRMD_0 COMP_E_CTL1_PWRMD_0 /*!< High-speed mode */ +#define CEPWRMD_1 COMP_E_CTL1_PWRMD_1 /*!< Normal mode */ +#define CEPWRMD_2 COMP_E_CTL1_PWRMD_2 /*!< Ultra-low power mode */ +/* CE0CTL1[CEON] Bits */ +#define CEON_OFS COMP_E_CTL1_ON_OFS /*!< CEON Offset */ +#define CEON COMP_E_CTL1_ON /*!< Comparator On */ +/* CE0CTL1[CEMRVL] Bits */ +#define CEMRVL_OFS COMP_E_CTL1_MRVL_OFS /*!< CEMRVL Offset */ +#define CEMRVL COMP_E_CTL1_MRVL /*!< This bit is valid of CEMRVS is set to 1 */ +/* CE0CTL1[CEMRVS] Bits */ +#define CEMRVS_OFS COMP_E_CTL1_MRVS_OFS /*!< CEMRVS Offset */ +#define CEMRVS COMP_E_CTL1_MRVS +/* CE0CTL2[CEREF0] Bits */ +#define CEREF0_OFS COMP_E_CTL2_REF0_OFS /*!< CEREF0 Offset */ +#define CEREF0_M COMP_E_CTL2_REF0_MASK /*!< Reference resistor tap 0 */ +#define CEREF00 COMP_E_CTL2_REF00 /*!< CEREF0 Bit 0 */ +#define CEREF01 COMP_E_CTL2_REF01 /*!< CEREF0 Bit 1 */ +#define CEREF02 COMP_E_CTL2_REF02 /*!< CEREF0 Bit 2 */ +#define CEREF03 COMP_E_CTL2_REF03 /*!< CEREF0 Bit 3 */ +#define CEREF04 COMP_E_CTL2_REF04 /*!< CEREF0 Bit 4 */ +#define CEREF0_0 COMP_E_CTL2_REF0_0 /*!< Reference resistor tap for setting 0. */ +#define CEREF0_1 COMP_E_CTL2_REF0_1 /*!< Reference resistor tap for setting 1. */ +#define CEREF0_2 COMP_E_CTL2_REF0_2 /*!< Reference resistor tap for setting 2. */ +#define CEREF0_3 COMP_E_CTL2_REF0_3 /*!< Reference resistor tap for setting 3. */ +#define CEREF0_4 COMP_E_CTL2_REF0_4 /*!< Reference resistor tap for setting 4. */ +#define CEREF0_5 COMP_E_CTL2_REF0_5 /*!< Reference resistor tap for setting 5. */ +#define CEREF0_6 COMP_E_CTL2_REF0_6 /*!< Reference resistor tap for setting 6. */ +#define CEREF0_7 COMP_E_CTL2_REF0_7 /*!< Reference resistor tap for setting 7. */ +#define CEREF0_8 COMP_E_CTL2_REF0_8 /*!< Reference resistor tap for setting 8. */ +#define CEREF0_9 COMP_E_CTL2_REF0_9 /*!< Reference resistor tap for setting 9. */ +#define CEREF0_10 COMP_E_CTL2_REF0_10 /*!< Reference resistor tap for setting 10. */ +#define CEREF0_11 COMP_E_CTL2_REF0_11 /*!< Reference resistor tap for setting 11. */ +#define CEREF0_12 COMP_E_CTL2_REF0_12 /*!< Reference resistor tap for setting 12. */ +#define CEREF0_13 COMP_E_CTL2_REF0_13 /*!< Reference resistor tap for setting 13. */ +#define CEREF0_14 COMP_E_CTL2_REF0_14 /*!< Reference resistor tap for setting 14. */ +#define CEREF0_15 COMP_E_CTL2_REF0_15 /*!< Reference resistor tap for setting 15. */ +#define CEREF0_16 COMP_E_CTL2_REF0_16 /*!< Reference resistor tap for setting 16. */ +#define CEREF0_17 COMP_E_CTL2_REF0_17 /*!< Reference resistor tap for setting 17. */ +#define CEREF0_18 COMP_E_CTL2_REF0_18 /*!< Reference resistor tap for setting 18. */ +#define CEREF0_19 COMP_E_CTL2_REF0_19 /*!< Reference resistor tap for setting 19. */ +#define CEREF0_20 COMP_E_CTL2_REF0_20 /*!< Reference resistor tap for setting 20. */ +#define CEREF0_21 COMP_E_CTL2_REF0_21 /*!< Reference resistor tap for setting 21. */ +#define CEREF0_22 COMP_E_CTL2_REF0_22 /*!< Reference resistor tap for setting 22. */ +#define CEREF0_23 COMP_E_CTL2_REF0_23 /*!< Reference resistor tap for setting 23. */ +#define CEREF0_24 COMP_E_CTL2_REF0_24 /*!< Reference resistor tap for setting 24. */ +#define CEREF0_25 COMP_E_CTL2_REF0_25 /*!< Reference resistor tap for setting 25. */ +#define CEREF0_26 COMP_E_CTL2_REF0_26 /*!< Reference resistor tap for setting 26. */ +#define CEREF0_27 COMP_E_CTL2_REF0_27 /*!< Reference resistor tap for setting 27. */ +#define CEREF0_28 COMP_E_CTL2_REF0_28 /*!< Reference resistor tap for setting 28. */ +#define CEREF0_29 COMP_E_CTL2_REF0_29 /*!< Reference resistor tap for setting 29. */ +#define CEREF0_30 COMP_E_CTL2_REF0_30 /*!< Reference resistor tap for setting 30. */ +#define CEREF0_31 COMP_E_CTL2_REF0_31 /*!< Reference resistor tap for setting 31. */ +/* CE0CTL2[CERSEL] Bits */ +#define CERSEL_OFS COMP_E_CTL2_RSEL_OFS /*!< CERSEL Offset */ +#define CERSEL COMP_E_CTL2_RSEL /*!< Reference select */ +/* CE0CTL2[CERS] Bits */ +#define CERS_OFS COMP_E_CTL2_RS_OFS /*!< CERS Offset */ +#define CERS_M COMP_E_CTL2_RS_MASK /*!< Reference source */ +#define CERS0 COMP_E_CTL2_RS0 /*!< CERS Bit 0 */ +#define CERS1 COMP_E_CTL2_RS1 /*!< CERS Bit 1 */ +#define CERS_0 COMP_E_CTL2_RS_0 /*!< No current is drawn by the reference circuitry */ +#define CERS_1 COMP_E_CTL2_RS_1 /*!< VCC applied to the resistor ladder */ +#define CERS_2 COMP_E_CTL2_RS_2 /*!< Shared reference voltage applied to the resistor ladder */ +#define CERS_3 COMP_E_CTL2_RS_3 /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ +/* CE0CTL2[CEREF1] Bits */ +#define CEREF1_OFS COMP_E_CTL2_REF1_OFS /*!< CEREF1 Offset */ +#define CEREF1_M COMP_E_CTL2_REF1_MASK /*!< Reference resistor tap 1 */ +#define CEREF10 COMP_E_CTL2_REF10 /*!< CEREF1 Bit 0 */ +#define CEREF11 COMP_E_CTL2_REF11 /*!< CEREF1 Bit 1 */ +#define CEREF12 COMP_E_CTL2_REF12 /*!< CEREF1 Bit 2 */ +#define CEREF13 COMP_E_CTL2_REF13 /*!< CEREF1 Bit 3 */ +#define CEREF14 COMP_E_CTL2_REF14 /*!< CEREF1 Bit 4 */ +#define CEREF1_0 COMP_E_CTL2_REF1_0 /*!< Reference resistor tap for setting 0. */ +#define CEREF1_1 COMP_E_CTL2_REF1_1 /*!< Reference resistor tap for setting 1. */ +#define CEREF1_2 COMP_E_CTL2_REF1_2 /*!< Reference resistor tap for setting 2. */ +#define CEREF1_3 COMP_E_CTL2_REF1_3 /*!< Reference resistor tap for setting 3. */ +#define CEREF1_4 COMP_E_CTL2_REF1_4 /*!< Reference resistor tap for setting 4. */ +#define CEREF1_5 COMP_E_CTL2_REF1_5 /*!< Reference resistor tap for setting 5. */ +#define CEREF1_6 COMP_E_CTL2_REF1_6 /*!< Reference resistor tap for setting 6. */ +#define CEREF1_7 COMP_E_CTL2_REF1_7 /*!< Reference resistor tap for setting 7. */ +#define CEREF1_8 COMP_E_CTL2_REF1_8 /*!< Reference resistor tap for setting 8. */ +#define CEREF1_9 COMP_E_CTL2_REF1_9 /*!< Reference resistor tap for setting 9. */ +#define CEREF1_10 COMP_E_CTL2_REF1_10 /*!< Reference resistor tap for setting 10. */ +#define CEREF1_11 COMP_E_CTL2_REF1_11 /*!< Reference resistor tap for setting 11. */ +#define CEREF1_12 COMP_E_CTL2_REF1_12 /*!< Reference resistor tap for setting 12. */ +#define CEREF1_13 COMP_E_CTL2_REF1_13 /*!< Reference resistor tap for setting 13. */ +#define CEREF1_14 COMP_E_CTL2_REF1_14 /*!< Reference resistor tap for setting 14. */ +#define CEREF1_15 COMP_E_CTL2_REF1_15 /*!< Reference resistor tap for setting 15. */ +#define CEREF1_16 COMP_E_CTL2_REF1_16 /*!< Reference resistor tap for setting 16. */ +#define CEREF1_17 COMP_E_CTL2_REF1_17 /*!< Reference resistor tap for setting 17. */ +#define CEREF1_18 COMP_E_CTL2_REF1_18 /*!< Reference resistor tap for setting 18. */ +#define CEREF1_19 COMP_E_CTL2_REF1_19 /*!< Reference resistor tap for setting 19. */ +#define CEREF1_20 COMP_E_CTL2_REF1_20 /*!< Reference resistor tap for setting 20. */ +#define CEREF1_21 COMP_E_CTL2_REF1_21 /*!< Reference resistor tap for setting 21. */ +#define CEREF1_22 COMP_E_CTL2_REF1_22 /*!< Reference resistor tap for setting 22. */ +#define CEREF1_23 COMP_E_CTL2_REF1_23 /*!< Reference resistor tap for setting 23. */ +#define CEREF1_24 COMP_E_CTL2_REF1_24 /*!< Reference resistor tap for setting 24. */ +#define CEREF1_25 COMP_E_CTL2_REF1_25 /*!< Reference resistor tap for setting 25. */ +#define CEREF1_26 COMP_E_CTL2_REF1_26 /*!< Reference resistor tap for setting 26. */ +#define CEREF1_27 COMP_E_CTL2_REF1_27 /*!< Reference resistor tap for setting 27. */ +#define CEREF1_28 COMP_E_CTL2_REF1_28 /*!< Reference resistor tap for setting 28. */ +#define CEREF1_29 COMP_E_CTL2_REF1_29 /*!< Reference resistor tap for setting 29. */ +#define CEREF1_30 COMP_E_CTL2_REF1_30 /*!< Reference resistor tap for setting 30. */ +#define CEREF1_31 COMP_E_CTL2_REF1_31 /*!< Reference resistor tap for setting 31. */ +/* CE0CTL2[CEREFL] Bits */ +#define CEREFL_OFS COMP_E_CTL2_REFL_OFS /*!< CEREFL Offset */ +#define CEREFL_M COMP_E_CTL2_REFL_MASK /*!< Reference voltage level */ +#define CEREFL0 COMP_E_CTL2_REFL0 /*!< CEREFL Bit 0 */ +#define CEREFL1 COMP_E_CTL2_REFL1 /*!< CEREFL Bit 1 */ +#define CEREFL_0 COMP_E_CTL2_CEREFL_0 /*!< Reference amplifier is disabled. No reference voltage is requested */ +#define CEREFL_1 COMP_E_CTL2_CEREFL_1 /*!< 1.2 V is selected as shared reference voltage input */ +#define CEREFL_2 COMP_E_CTL2_CEREFL_2 /*!< 2.0 V is selected as shared reference voltage input */ +#define CEREFL_3 COMP_E_CTL2_CEREFL_3 /*!< 2.5 V is selected as shared reference voltage input */ +#define CEREFL__OFF COMP_E_CTL2_REFL__OFF /*!< Reference amplifier is disabled. No reference voltage is requested */ +#define CEREFL__1P2V COMP_E_CTL2_REFL__1P2V /*!< 1.2 V is selected as shared reference voltage input */ +#define CEREFL__2P0V COMP_E_CTL2_REFL__2P0V /*!< 2.0 V is selected as shared reference voltage input */ +#define CEREFL__2P5V COMP_E_CTL2_REFL__2P5V /*!< 2.5 V is selected as shared reference voltage input */ +/* CE0CTL2[CEREFACC] Bits */ +#define CEREFACC_OFS COMP_E_CTL2_REFACC_OFS /*!< CEREFACC Offset */ +#define CEREFACC COMP_E_CTL2_REFACC /*!< Reference accuracy */ +/* CE0CTL3[CEPD0] Bits */ +#define CEPD0_OFS COMP_E_CTL3_PD0_OFS /*!< CEPD0 Offset */ +#define CEPD0 COMP_E_CTL3_PD0 /*!< Port disable */ +/* CE0CTL3[CEPD1] Bits */ +#define CEPD1_OFS COMP_E_CTL3_PD1_OFS /*!< CEPD1 Offset */ +#define CEPD1 COMP_E_CTL3_PD1 /*!< Port disable */ +/* CE0CTL3[CEPD2] Bits */ +#define CEPD2_OFS COMP_E_CTL3_PD2_OFS /*!< CEPD2 Offset */ +#define CEPD2 COMP_E_CTL3_PD2 /*!< Port disable */ +/* CE0CTL3[CEPD3] Bits */ +#define CEPD3_OFS COMP_E_CTL3_PD3_OFS /*!< CEPD3 Offset */ +#define CEPD3 COMP_E_CTL3_PD3 /*!< Port disable */ +/* CE0CTL3[CEPD4] Bits */ +#define CEPD4_OFS COMP_E_CTL3_PD4_OFS /*!< CEPD4 Offset */ +#define CEPD4 COMP_E_CTL3_PD4 /*!< Port disable */ +/* CE0CTL3[CEPD5] Bits */ +#define CEPD5_OFS COMP_E_CTL3_PD5_OFS /*!< CEPD5 Offset */ +#define CEPD5 COMP_E_CTL3_PD5 /*!< Port disable */ +/* CE0CTL3[CEPD6] Bits */ +#define CEPD6_OFS COMP_E_CTL3_PD6_OFS /*!< CEPD6 Offset */ +#define CEPD6 COMP_E_CTL3_PD6 /*!< Port disable */ +/* CE0CTL3[CEPD7] Bits */ +#define CEPD7_OFS COMP_E_CTL3_PD7_OFS /*!< CEPD7 Offset */ +#define CEPD7 COMP_E_CTL3_PD7 /*!< Port disable */ +/* CE0CTL3[CEPD8] Bits */ +#define CEPD8_OFS COMP_E_CTL3_PD8_OFS /*!< CEPD8 Offset */ +#define CEPD8 COMP_E_CTL3_PD8 /*!< Port disable */ +/* CE0CTL3[CEPD9] Bits */ +#define CEPD9_OFS COMP_E_CTL3_PD9_OFS /*!< CEPD9 Offset */ +#define CEPD9 COMP_E_CTL3_PD9 /*!< Port disable */ +/* CE0CTL3[CEPD10] Bits */ +#define CEPD10_OFS COMP_E_CTL3_PD10_OFS /*!< CEPD10 Offset */ +#define CEPD10 COMP_E_CTL3_PD10 /*!< Port disable */ +/* CE0CTL3[CEPD11] Bits */ +#define CEPD11_OFS COMP_E_CTL3_PD11_OFS /*!< CEPD11 Offset */ +#define CEPD11 COMP_E_CTL3_PD11 /*!< Port disable */ +/* CE0CTL3[CEPD12] Bits */ +#define CEPD12_OFS COMP_E_CTL3_PD12_OFS /*!< CEPD12 Offset */ +#define CEPD12 COMP_E_CTL3_PD12 /*!< Port disable */ +/* CE0CTL3[CEPD13] Bits */ +#define CEPD13_OFS COMP_E_CTL3_PD13_OFS /*!< CEPD13 Offset */ +#define CEPD13 COMP_E_CTL3_PD13 /*!< Port disable */ +/* CE0CTL3[CEPD14] Bits */ +#define CEPD14_OFS COMP_E_CTL3_PD14_OFS /*!< CEPD14 Offset */ +#define CEPD14 COMP_E_CTL3_PD14 /*!< Port disable */ +/* CE0CTL3[CEPD15] Bits */ +#define CEPD15_OFS COMP_E_CTL3_PD15_OFS /*!< CEPD15 Offset */ +#define CEPD15 COMP_E_CTL3_PD15 /*!< Port disable */ +/* CE0INT[CEIFG] Bits */ +#define CEIFG_OFS COMP_E_INT_IFG_OFS /*!< CEIFG Offset */ +#define CEIFG COMP_E_INT_IFG /*!< Comparator output interrupt flag */ +/* CE0INT[CEIIFG] Bits */ +#define CEIIFG_OFS COMP_E_INT_IIFG_OFS /*!< CEIIFG Offset */ +#define CEIIFG COMP_E_INT_IIFG /*!< Comparator output inverted interrupt flag */ +/* CE0INT[CERDYIFG] Bits */ +#define CERDYIFG_OFS COMP_E_INT_RDYIFG_OFS /*!< CERDYIFG Offset */ +#define CERDYIFG COMP_E_INT_RDYIFG /*!< Comparator ready interrupt flag */ +/* CE0INT[CEIE] Bits */ +#define CEIE_OFS COMP_E_INT_IE_OFS /*!< CEIE Offset */ +#define CEIE COMP_E_INT_IE /*!< Comparator output interrupt enable */ +/* CE0INT[CEIIE] Bits */ +#define CEIIE_OFS COMP_E_INT_IIE_OFS /*!< CEIIE Offset */ +#define CEIIE COMP_E_INT_IIE /*!< Comparator output interrupt enable inverted polarity */ +/* CE0INT[CERDYIE] Bits */ +#define CERDYIE_OFS COMP_E_INT_RDYIE_OFS /*!< CERDYIE Offset */ +#define CERDYIE COMP_E_INT_RDYIE /*!< Comparator ready interrupt enable */ + +/****************************************************************************** +* CRC32 Bits (legacy section) +******************************************************************************/ +/* DIO_PAIN[P1IN] Bits */ +#define P1IN_OFS ( 0) /*!< P1IN Offset */ +#define P1IN_M (0x00ff) /*!< Port 1 Input */ +/* DIO_PAIN[P2IN] Bits */ +#define P2IN_OFS ( 8) /*!< P2IN Offset */ +#define P2IN_M (0xff00) /*!< Port 2 Input */ +/* DIO_PAOUT[P2OUT] Bits */ +#define P2OUT_OFS ( 8) /*!< P2OUT Offset */ +#define P2OUT_M (0xff00) /*!< Port 2 Output */ +/* DIO_PAOUT[P1OUT] Bits */ +#define P1OUT_OFS ( 0) /*!< P1OUT Offset */ +#define P1OUT_M (0x00ff) /*!< Port 1 Output */ +/* DIO_PADIR[P1DIR] Bits */ +#define P1DIR_OFS ( 0) /*!< P1DIR Offset */ +#define P1DIR_M (0x00ff) /*!< Port 1 Direction */ +/* DIO_PADIR[P2DIR] Bits */ +#define P2DIR_OFS ( 8) /*!< P2DIR Offset */ +#define P2DIR_M (0xff00) /*!< Port 2 Direction */ +/* DIO_PAREN[P1REN] Bits */ +#define P1REN_OFS ( 0) /*!< P1REN Offset */ +#define P1REN_M (0x00ff) /*!< Port 1 Resistor Enable */ +/* DIO_PAREN[P2REN] Bits */ +#define P2REN_OFS ( 8) /*!< P2REN Offset */ +#define P2REN_M (0xff00) /*!< Port 2 Resistor Enable */ +/* DIO_PADS[P1DS] Bits */ +#define P1DS_OFS ( 0) /*!< P1DS Offset */ +#define P1DS_M (0x00ff) /*!< Port 1 Drive Strength */ +/* DIO_PADS[P2DS] Bits */ +#define P2DS_OFS ( 8) /*!< P2DS Offset */ +#define P2DS_M (0xff00) /*!< Port 2 Drive Strength */ +/* DIO_PASEL0[P1SEL0] Bits */ +#define P1SEL0_OFS ( 0) /*!< P1SEL0 Offset */ +#define P1SEL0_M (0x00ff) /*!< Port 1 Select 0 */ +/* DIO_PASEL0[P2SEL0] Bits */ +#define P2SEL0_OFS ( 8) /*!< P2SEL0 Offset */ +#define P2SEL0_M (0xff00) /*!< Port 2 Select 0 */ +/* DIO_PASEL1[P1SEL1] Bits */ +#define P1SEL1_OFS ( 0) /*!< P1SEL1 Offset */ +#define P1SEL1_M (0x00ff) /*!< Port 1 Select 1 */ +/* DIO_PASEL1[P2SEL1] Bits */ +#define P2SEL1_OFS ( 8) /*!< P2SEL1 Offset */ +#define P2SEL1_M (0xff00) /*!< Port 2 Select 1 */ +/* DIO_P1IV[P1IV] Bits */ +#define P1IV_OFS ( 0) /*!< P1IV Offset */ +#define P1IV_M (0x001f) /*!< Port 1 interrupt vector value */ +#define P1IV0 (0x0001) /*!< Port 1 interrupt vector value */ +#define P1IV1 (0x0002) /*!< Port 1 interrupt vector value */ +#define P1IV2 (0x0004) /*!< Port 1 interrupt vector value */ +#define P1IV3 (0x0008) /*!< Port 1 interrupt vector value */ +#define P1IV4 (0x0010) /*!< Port 1 interrupt vector value */ +#define P1IV_0 (0x0000) /*!< No interrupt pending */ +#define P1IV_2 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ +#define P1IV_4 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ +#define P1IV_6 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ +#define P1IV_8 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ +#define P1IV_10 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ +#define P1IV_12 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ +#define P1IV_14 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ +#define P1IV_16 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ +#define P1IV__NONE (0x0000) /*!< No interrupt pending */ +#define P1IV__P1IFG0 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ +#define P1IV__P1IFG1 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ +#define P1IV__P1IFG2 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ +#define P1IV__P1IFG3 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ +#define P1IV__P1IFG4 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ +#define P1IV__P1IFG5 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ +#define P1IV__P1IFG6 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ +#define P1IV__P1IFG7 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ +/* DIO_PASELC[P1SELC] Bits */ +#define P1SELC_OFS ( 0) /*!< P1SELC Offset */ +#define P1SELC_M (0x00ff) /*!< Port 1 Complement Select */ +/* DIO_PASELC[P2SELC] Bits */ +#define P2SELC_OFS ( 8) /*!< P2SELC Offset */ +#define P2SELC_M (0xff00) /*!< Port 2 Complement Select */ +/* DIO_PAIES[P1IES] Bits */ +#define P1IES_OFS ( 0) /*!< P1IES Offset */ +#define P1IES_M (0x00ff) /*!< Port 1 Interrupt Edge Select */ +/* DIO_PAIES[P2IES] Bits */ +#define P2IES_OFS ( 8) /*!< P2IES Offset */ +#define P2IES_M (0xff00) /*!< Port 2 Interrupt Edge Select */ +/* DIO_PAIE[P1IE] Bits */ +#define P1IE_OFS ( 0) /*!< P1IE Offset */ +#define P1IE_M (0x00ff) /*!< Port 1 Interrupt Enable */ +/* DIO_PAIE[P2IE] Bits */ +#define P2IE_OFS ( 8) /*!< P2IE Offset */ +#define P2IE_M (0xff00) /*!< Port 2 Interrupt Enable */ +/* DIO_PAIFG[P1IFG] Bits */ +#define P1IFG_OFS ( 0) /*!< P1IFG Offset */ +#define P1IFG_M (0x00ff) /*!< Port 1 Interrupt Flag */ +/* DIO_PAIFG[P2IFG] Bits */ +#define P2IFG_OFS ( 8) /*!< P2IFG Offset */ +#define P2IFG_M (0xff00) /*!< Port 2 Interrupt Flag */ +/* DIO_P2IV[P2IV] Bits */ +#define P2IV_OFS ( 0) /*!< P2IV Offset */ +#define P2IV_M (0x001f) /*!< Port 2 interrupt vector value */ +#define P2IV0 (0x0001) /*!< Port 2 interrupt vector value */ +#define P2IV1 (0x0002) /*!< Port 2 interrupt vector value */ +#define P2IV2 (0x0004) /*!< Port 2 interrupt vector value */ +#define P2IV3 (0x0008) /*!< Port 2 interrupt vector value */ +#define P2IV4 (0x0010) /*!< Port 2 interrupt vector value */ +#define P2IV_0 (0x0000) /*!< No interrupt pending */ +#define P2IV_2 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ +#define P2IV_4 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ +#define P2IV_6 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ +#define P2IV_8 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ +#define P2IV_10 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ +#define P2IV_12 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ +#define P2IV_14 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ +#define P2IV_16 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ +#define P2IV__NONE (0x0000) /*!< No interrupt pending */ +#define P2IV__P2IFG0 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ +#define P2IV__P2IFG1 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ +#define P2IV__P2IFG2 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ +#define P2IV__P2IFG3 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ +#define P2IV__P2IFG4 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ +#define P2IV__P2IFG5 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ +#define P2IV__P2IFG6 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ +#define P2IV__P2IFG7 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ +/* DIO_PBIN[P3IN] Bits */ +#define P3IN_OFS ( 0) /*!< P3IN Offset */ +#define P3IN_M (0x00ff) /*!< Port 3 Input */ +/* DIO_PBIN[P4IN] Bits */ +#define P4IN_OFS ( 8) /*!< P4IN Offset */ +#define P4IN_M (0xff00) /*!< Port 4 Input */ +/* DIO_PBOUT[P3OUT] Bits */ +#define P3OUT_OFS ( 0) /*!< P3OUT Offset */ +#define P3OUT_M (0x00ff) /*!< Port 3 Output */ +/* DIO_PBOUT[P4OUT] Bits */ +#define P4OUT_OFS ( 8) /*!< P4OUT Offset */ +#define P4OUT_M (0xff00) /*!< Port 4 Output */ +/* DIO_PBDIR[P3DIR] Bits */ +#define P3DIR_OFS ( 0) /*!< P3DIR Offset */ +#define P3DIR_M (0x00ff) /*!< Port 3 Direction */ +/* DIO_PBDIR[P4DIR] Bits */ +#define P4DIR_OFS ( 8) /*!< P4DIR Offset */ +#define P4DIR_M (0xff00) /*!< Port 4 Direction */ +/* DIO_PBREN[P3REN] Bits */ +#define P3REN_OFS ( 0) /*!< P3REN Offset */ +#define P3REN_M (0x00ff) /*!< Port 3 Resistor Enable */ +/* DIO_PBREN[P4REN] Bits */ +#define P4REN_OFS ( 8) /*!< P4REN Offset */ +#define P4REN_M (0xff00) /*!< Port 4 Resistor Enable */ +/* DIO_PBDS[P3DS] Bits */ +#define P3DS_OFS ( 0) /*!< P3DS Offset */ +#define P3DS_M (0x00ff) /*!< Port 3 Drive Strength */ +/* DIO_PBDS[P4DS] Bits */ +#define P4DS_OFS ( 8) /*!< P4DS Offset */ +#define P4DS_M (0xff00) /*!< Port 4 Drive Strength */ +/* DIO_PBSEL0[P4SEL0] Bits */ +#define P4SEL0_OFS ( 8) /*!< P4SEL0 Offset */ +#define P4SEL0_M (0xff00) /*!< Port 4 Select 0 */ +/* DIO_PBSEL0[P3SEL0] Bits */ +#define P3SEL0_OFS ( 0) /*!< P3SEL0 Offset */ +#define P3SEL0_M (0x00ff) /*!< Port 3 Select 0 */ +/* DIO_PBSEL1[P3SEL1] Bits */ +#define P3SEL1_OFS ( 0) /*!< P3SEL1 Offset */ +#define P3SEL1_M (0x00ff) /*!< Port 3 Select 1 */ +/* DIO_PBSEL1[P4SEL1] Bits */ +#define P4SEL1_OFS ( 8) /*!< P4SEL1 Offset */ +#define P4SEL1_M (0xff00) /*!< Port 4 Select 1 */ +/* DIO_P3IV[P3IV] Bits */ +#define P3IV_OFS ( 0) /*!< P3IV Offset */ +#define P3IV_M (0x001f) /*!< Port 3 interrupt vector value */ +#define P3IV0 (0x0001) /*!< Port 3 interrupt vector value */ +#define P3IV1 (0x0002) /*!< Port 3 interrupt vector value */ +#define P3IV2 (0x0004) /*!< Port 3 interrupt vector value */ +#define P3IV3 (0x0008) /*!< Port 3 interrupt vector value */ +#define P3IV4 (0x0010) /*!< Port 3 interrupt vector value */ +#define P3IV_0 (0x0000) /*!< No interrupt pending */ +#define P3IV_2 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ +#define P3IV_4 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ +#define P3IV_6 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ +#define P3IV_8 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ +#define P3IV_10 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ +#define P3IV_12 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ +#define P3IV_14 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ +#define P3IV_16 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ +#define P3IV__NONE (0x0000) /*!< No interrupt pending */ +#define P3IV__P3IFG0 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ +#define P3IV__P3IFG1 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ +#define P3IV__P3IFG2 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ +#define P3IV__P3IFG3 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ +#define P3IV__P3IFG4 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ +#define P3IV__P3IFG5 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ +#define P3IV__P3IFG6 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ +#define P3IV__P3IFG7 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ +/* DIO_PBSELC[P3SELC] Bits */ +#define P3SELC_OFS ( 0) /*!< P3SELC Offset */ +#define P3SELC_M (0x00ff) /*!< Port 3 Complement Select */ +/* DIO_PBSELC[P4SELC] Bits */ +#define P4SELC_OFS ( 8) /*!< P4SELC Offset */ +#define P4SELC_M (0xff00) /*!< Port 4 Complement Select */ +/* DIO_PBIES[P3IES] Bits */ +#define P3IES_OFS ( 0) /*!< P3IES Offset */ +#define P3IES_M (0x00ff) /*!< Port 3 Interrupt Edge Select */ +/* DIO_PBIES[P4IES] Bits */ +#define P4IES_OFS ( 8) /*!< P4IES Offset */ +#define P4IES_M (0xff00) /*!< Port 4 Interrupt Edge Select */ +/* DIO_PBIE[P3IE] Bits */ +#define P3IE_OFS ( 0) /*!< P3IE Offset */ +#define P3IE_M (0x00ff) /*!< Port 3 Interrupt Enable */ +/* DIO_PBIE[P4IE] Bits */ +#define P4IE_OFS ( 8) /*!< P4IE Offset */ +#define P4IE_M (0xff00) /*!< Port 4 Interrupt Enable */ +/* DIO_PBIFG[P3IFG] Bits */ +#define P3IFG_OFS ( 0) /*!< P3IFG Offset */ +#define P3IFG_M (0x00ff) /*!< Port 3 Interrupt Flag */ +/* DIO_PBIFG[P4IFG] Bits */ +#define P4IFG_OFS ( 8) /*!< P4IFG Offset */ +#define P4IFG_M (0xff00) /*!< Port 4 Interrupt Flag */ +/* DIO_P4IV[P4IV] Bits */ +#define P4IV_OFS ( 0) /*!< P4IV Offset */ +#define P4IV_M (0x001f) /*!< Port 4 interrupt vector value */ +#define P4IV0 (0x0001) /*!< Port 4 interrupt vector value */ +#define P4IV1 (0x0002) /*!< Port 4 interrupt vector value */ +#define P4IV2 (0x0004) /*!< Port 4 interrupt vector value */ +#define P4IV3 (0x0008) /*!< Port 4 interrupt vector value */ +#define P4IV4 (0x0010) /*!< Port 4 interrupt vector value */ +#define P4IV_0 (0x0000) /*!< No interrupt pending */ +#define P4IV_2 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ +#define P4IV_4 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ +#define P4IV_6 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ +#define P4IV_8 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ +#define P4IV_10 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ +#define P4IV_12 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ +#define P4IV_14 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ +#define P4IV_16 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ +#define P4IV__NONE (0x0000) /*!< No interrupt pending */ +#define P4IV__P4IFG0 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ +#define P4IV__P4IFG1 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ +#define P4IV__P4IFG2 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ +#define P4IV__P4IFG3 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ +#define P4IV__P4IFG4 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ +#define P4IV__P4IFG5 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ +#define P4IV__P4IFG6 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ +#define P4IV__P4IFG7 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ +/* DIO_PCIN[P5IN] Bits */ +#define P5IN_OFS ( 0) /*!< P5IN Offset */ +#define P5IN_M (0x00ff) /*!< Port 5 Input */ +/* DIO_PCIN[P6IN] Bits */ +#define P6IN_OFS ( 8) /*!< P6IN Offset */ +#define P6IN_M (0xff00) /*!< Port 6 Input */ +/* DIO_PCOUT[P5OUT] Bits */ +#define P5OUT_OFS ( 0) /*!< P5OUT Offset */ +#define P5OUT_M (0x00ff) /*!< Port 5 Output */ +/* DIO_PCOUT[P6OUT] Bits */ +#define P6OUT_OFS ( 8) /*!< P6OUT Offset */ +#define P6OUT_M (0xff00) /*!< Port 6 Output */ +/* DIO_PCDIR[P5DIR] Bits */ +#define P5DIR_OFS ( 0) /*!< P5DIR Offset */ +#define P5DIR_M (0x00ff) /*!< Port 5 Direction */ +/* DIO_PCDIR[P6DIR] Bits */ +#define P6DIR_OFS ( 8) /*!< P6DIR Offset */ +#define P6DIR_M (0xff00) /*!< Port 6 Direction */ +/* DIO_PCREN[P5REN] Bits */ +#define P5REN_OFS ( 0) /*!< P5REN Offset */ +#define P5REN_M (0x00ff) /*!< Port 5 Resistor Enable */ +/* DIO_PCREN[P6REN] Bits */ +#define P6REN_OFS ( 8) /*!< P6REN Offset */ +#define P6REN_M (0xff00) /*!< Port 6 Resistor Enable */ +/* DIO_PCDS[P5DS] Bits */ +#define P5DS_OFS ( 0) /*!< P5DS Offset */ +#define P5DS_M (0x00ff) /*!< Port 5 Drive Strength */ +/* DIO_PCDS[P6DS] Bits */ +#define P6DS_OFS ( 8) /*!< P6DS Offset */ +#define P6DS_M (0xff00) /*!< Port 6 Drive Strength */ +/* DIO_PCSEL0[P5SEL0] Bits */ +#define P5SEL0_OFS ( 0) /*!< P5SEL0 Offset */ +#define P5SEL0_M (0x00ff) /*!< Port 5 Select 0 */ +/* DIO_PCSEL0[P6SEL0] Bits */ +#define P6SEL0_OFS ( 8) /*!< P6SEL0 Offset */ +#define P6SEL0_M (0xff00) /*!< Port 6 Select 0 */ +/* DIO_PCSEL1[P5SEL1] Bits */ +#define P5SEL1_OFS ( 0) /*!< P5SEL1 Offset */ +#define P5SEL1_M (0x00ff) /*!< Port 5 Select 1 */ +/* DIO_PCSEL1[P6SEL1] Bits */ +#define P6SEL1_OFS ( 8) /*!< P6SEL1 Offset */ +#define P6SEL1_M (0xff00) /*!< Port 6 Select 1 */ +/* DIO_P5IV[P5IV] Bits */ +#define P5IV_OFS ( 0) /*!< P5IV Offset */ +#define P5IV_M (0x001f) /*!< Port 5 interrupt vector value */ +#define P5IV0 (0x0001) /*!< Port 5 interrupt vector value */ +#define P5IV1 (0x0002) /*!< Port 5 interrupt vector value */ +#define P5IV2 (0x0004) /*!< Port 5 interrupt vector value */ +#define P5IV3 (0x0008) /*!< Port 5 interrupt vector value */ +#define P5IV4 (0x0010) /*!< Port 5 interrupt vector value */ +#define P5IV_0 (0x0000) /*!< No interrupt pending */ +#define P5IV_2 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ +#define P5IV_4 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ +#define P5IV_6 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ +#define P5IV_8 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ +#define P5IV_10 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ +#define P5IV_12 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ +#define P5IV_14 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ +#define P5IV_16 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ +#define P5IV__NONE (0x0000) /*!< No interrupt pending */ +#define P5IV__P5IFG0 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ +#define P5IV__P5IFG1 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ +#define P5IV__P5IFG2 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ +#define P5IV__P5IFG3 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ +#define P5IV__P5IFG4 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ +#define P5IV__P5IFG5 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ +#define P5IV__P5IFG6 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ +#define P5IV__P5IFG7 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ +/* DIO_PCSELC[P5SELC] Bits */ +#define P5SELC_OFS ( 0) /*!< P5SELC Offset */ +#define P5SELC_M (0x00ff) /*!< Port 5 Complement Select */ +/* DIO_PCSELC[P6SELC] Bits */ +#define P6SELC_OFS ( 8) /*!< P6SELC Offset */ +#define P6SELC_M (0xff00) /*!< Port 6 Complement Select */ +/* DIO_PCIES[P5IES] Bits */ +#define P5IES_OFS ( 0) /*!< P5IES Offset */ +#define P5IES_M (0x00ff) /*!< Port 5 Interrupt Edge Select */ +/* DIO_PCIES[P6IES] Bits */ +#define P6IES_OFS ( 8) /*!< P6IES Offset */ +#define P6IES_M (0xff00) /*!< Port 6 Interrupt Edge Select */ +/* DIO_PCIE[P5IE] Bits */ +#define P5IE_OFS ( 0) /*!< P5IE Offset */ +#define P5IE_M (0x00ff) /*!< Port 5 Interrupt Enable */ +/* DIO_PCIE[P6IE] Bits */ +#define P6IE_OFS ( 8) /*!< P6IE Offset */ +#define P6IE_M (0xff00) /*!< Port 6 Interrupt Enable */ +/* DIO_PCIFG[P5IFG] Bits */ +#define P5IFG_OFS ( 0) /*!< P5IFG Offset */ +#define P5IFG_M (0x00ff) /*!< Port 5 Interrupt Flag */ +/* DIO_PCIFG[P6IFG] Bits */ +#define P6IFG_OFS ( 8) /*!< P6IFG Offset */ +#define P6IFG_M (0xff00) /*!< Port 6 Interrupt Flag */ +/* DIO_P6IV[P6IV] Bits */ +#define P6IV_OFS ( 0) /*!< P6IV Offset */ +#define P6IV_M (0x001f) /*!< Port 6 interrupt vector value */ +#define P6IV0 (0x0001) /*!< Port 6 interrupt vector value */ +#define P6IV1 (0x0002) /*!< Port 6 interrupt vector value */ +#define P6IV2 (0x0004) /*!< Port 6 interrupt vector value */ +#define P6IV3 (0x0008) /*!< Port 6 interrupt vector value */ +#define P6IV4 (0x0010) /*!< Port 6 interrupt vector value */ +#define P6IV_0 (0x0000) /*!< No interrupt pending */ +#define P6IV_2 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ +#define P6IV_4 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ +#define P6IV_6 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ +#define P6IV_8 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ +#define P6IV_10 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ +#define P6IV_12 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ +#define P6IV_14 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ +#define P6IV_16 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ +#define P6IV__NONE (0x0000) /*!< No interrupt pending */ +#define P6IV__P6IFG0 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ +#define P6IV__P6IFG1 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ +#define P6IV__P6IFG2 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ +#define P6IV__P6IFG3 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ +#define P6IV__P6IFG4 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ +#define P6IV__P6IFG5 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ +#define P6IV__P6IFG6 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ +#define P6IV__P6IFG7 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ +/* DIO_PDIN[P7IN] Bits */ +#define P7IN_OFS ( 0) /*!< P7IN Offset */ +#define P7IN_M (0x00ff) /*!< Port 7 Input */ +/* DIO_PDIN[P8IN] Bits */ +#define P8IN_OFS ( 8) /*!< P8IN Offset */ +#define P8IN_M (0xff00) /*!< Port 8 Input */ +/* DIO_PDOUT[P7OUT] Bits */ +#define P7OUT_OFS ( 0) /*!< P7OUT Offset */ +#define P7OUT_M (0x00ff) /*!< Port 7 Output */ +/* DIO_PDOUT[P8OUT] Bits */ +#define P8OUT_OFS ( 8) /*!< P8OUT Offset */ +#define P8OUT_M (0xff00) /*!< Port 8 Output */ +/* DIO_PDDIR[P7DIR] Bits */ +#define P7DIR_OFS ( 0) /*!< P7DIR Offset */ +#define P7DIR_M (0x00ff) /*!< Port 7 Direction */ +/* DIO_PDDIR[P8DIR] Bits */ +#define P8DIR_OFS ( 8) /*!< P8DIR Offset */ +#define P8DIR_M (0xff00) /*!< Port 8 Direction */ +/* DIO_PDREN[P7REN] Bits */ +#define P7REN_OFS ( 0) /*!< P7REN Offset */ +#define P7REN_M (0x00ff) /*!< Port 7 Resistor Enable */ +/* DIO_PDREN[P8REN] Bits */ +#define P8REN_OFS ( 8) /*!< P8REN Offset */ +#define P8REN_M (0xff00) /*!< Port 8 Resistor Enable */ +/* DIO_PDDS[P7DS] Bits */ +#define P7DS_OFS ( 0) /*!< P7DS Offset */ +#define P7DS_M (0x00ff) /*!< Port 7 Drive Strength */ +/* DIO_PDDS[P8DS] Bits */ +#define P8DS_OFS ( 8) /*!< P8DS Offset */ +#define P8DS_M (0xff00) /*!< Port 8 Drive Strength */ +/* DIO_PDSEL0[P7SEL0] Bits */ +#define P7SEL0_OFS ( 0) /*!< P7SEL0 Offset */ +#define P7SEL0_M (0x00ff) /*!< Port 7 Select 0 */ +/* DIO_PDSEL0[P8SEL0] Bits */ +#define P8SEL0_OFS ( 8) /*!< P8SEL0 Offset */ +#define P8SEL0_M (0xff00) /*!< Port 8 Select 0 */ +/* DIO_PDSEL1[P7SEL1] Bits */ +#define P7SEL1_OFS ( 0) /*!< P7SEL1 Offset */ +#define P7SEL1_M (0x00ff) /*!< Port 7 Select 1 */ +/* DIO_PDSEL1[P8SEL1] Bits */ +#define P8SEL1_OFS ( 8) /*!< P8SEL1 Offset */ +#define P8SEL1_M (0xff00) /*!< Port 8 Select 1 */ +/* DIO_P7IV[P7IV] Bits */ +#define P7IV_OFS ( 0) /*!< P7IV Offset */ +#define P7IV_M (0x001f) /*!< Port 7 interrupt vector value */ +#define P7IV0 (0x0001) /*!< Port 7 interrupt vector value */ +#define P7IV1 (0x0002) /*!< Port 7 interrupt vector value */ +#define P7IV2 (0x0004) /*!< Port 7 interrupt vector value */ +#define P7IV3 (0x0008) /*!< Port 7 interrupt vector value */ +#define P7IV4 (0x0010) /*!< Port 7 interrupt vector value */ +#define P7IV_0 (0x0000) /*!< No interrupt pending */ +#define P7IV_2 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ +#define P7IV_4 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ +#define P7IV_6 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ +#define P7IV_8 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ +#define P7IV_10 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ +#define P7IV_12 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ +#define P7IV_14 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ +#define P7IV_16 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ +#define P7IV__NONE (0x0000) /*!< No interrupt pending */ +#define P7IV__P7IFG0 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ +#define P7IV__P7IFG1 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ +#define P7IV__P7IFG2 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ +#define P7IV__P7IFG3 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ +#define P7IV__P7IFG4 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ +#define P7IV__P7IFG5 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ +#define P7IV__P7IFG6 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ +#define P7IV__P7IFG7 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ +/* DIO_PDSELC[P7SELC] Bits */ +#define P7SELC_OFS ( 0) /*!< P7SELC Offset */ +#define P7SELC_M (0x00ff) /*!< Port 7 Complement Select */ +/* DIO_PDSELC[P8SELC] Bits */ +#define P8SELC_OFS ( 8) /*!< P8SELC Offset */ +#define P8SELC_M (0xff00) /*!< Port 8 Complement Select */ +/* DIO_PDIES[P7IES] Bits */ +#define P7IES_OFS ( 0) /*!< P7IES Offset */ +#define P7IES_M (0x00ff) /*!< Port 7 Interrupt Edge Select */ +/* DIO_PDIES[P8IES] Bits */ +#define P8IES_OFS ( 8) /*!< P8IES Offset */ +#define P8IES_M (0xff00) /*!< Port 8 Interrupt Edge Select */ +/* DIO_PDIE[P7IE] Bits */ +#define P7IE_OFS ( 0) /*!< P7IE Offset */ +#define P7IE_M (0x00ff) /*!< Port 7 Interrupt Enable */ +/* DIO_PDIE[P8IE] Bits */ +#define P8IE_OFS ( 8) /*!< P8IE Offset */ +#define P8IE_M (0xff00) /*!< Port 8 Interrupt Enable */ +/* DIO_PDIFG[P7IFG] Bits */ +#define P7IFG_OFS ( 0) /*!< P7IFG Offset */ +#define P7IFG_M (0x00ff) /*!< Port 7 Interrupt Flag */ +/* DIO_PDIFG[P8IFG] Bits */ +#define P8IFG_OFS ( 8) /*!< P8IFG Offset */ +#define P8IFG_M (0xff00) /*!< Port 8 Interrupt Flag */ +/* DIO_P8IV[P8IV] Bits */ +#define P8IV_OFS ( 0) /*!< P8IV Offset */ +#define P8IV_M (0x001f) /*!< Port 8 interrupt vector value */ +#define P8IV0 (0x0001) /*!< Port 8 interrupt vector value */ +#define P8IV1 (0x0002) /*!< Port 8 interrupt vector value */ +#define P8IV2 (0x0004) /*!< Port 8 interrupt vector value */ +#define P8IV3 (0x0008) /*!< Port 8 interrupt vector value */ +#define P8IV4 (0x0010) /*!< Port 8 interrupt vector value */ +#define P8IV_0 (0x0000) /*!< No interrupt pending */ +#define P8IV_2 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ +#define P8IV_4 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ +#define P8IV_6 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ +#define P8IV_8 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ +#define P8IV_10 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ +#define P8IV_12 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ +#define P8IV_14 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ +#define P8IV_16 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ +#define P8IV__NONE (0x0000) /*!< No interrupt pending */ +#define P8IV__P8IFG0 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ +#define P8IV__P8IFG1 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ +#define P8IV__P8IFG2 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ +#define P8IV__P8IFG3 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ +#define P8IV__P8IFG4 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ +#define P8IV__P8IFG5 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ +#define P8IV__P8IFG6 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ +#define P8IV__P8IFG7 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ +/* DIO_PEIN[P9IN] Bits */ +#define P9IN_OFS ( 0) /*!< P9IN Offset */ +#define P9IN_M (0x00ff) /*!< Port 9 Input */ +/* DIO_PEIN[P10IN] Bits */ +#define P10IN_OFS ( 8) /*!< P10IN Offset */ +#define P10IN_M (0xff00) /*!< Port 10 Input */ +/* DIO_PEOUT[P9OUT] Bits */ +#define P9OUT_OFS ( 0) /*!< P9OUT Offset */ +#define P9OUT_M (0x00ff) /*!< Port 9 Output */ +/* DIO_PEOUT[P10OUT] Bits */ +#define P10OUT_OFS ( 8) /*!< P10OUT Offset */ +#define P10OUT_M (0xff00) /*!< Port 10 Output */ +/* DIO_PEDIR[P9DIR] Bits */ +#define P9DIR_OFS ( 0) /*!< P9DIR Offset */ +#define P9DIR_M (0x00ff) /*!< Port 9 Direction */ +/* DIO_PEDIR[P10DIR] Bits */ +#define P10DIR_OFS ( 8) /*!< P10DIR Offset */ +#define P10DIR_M (0xff00) /*!< Port 10 Direction */ +/* DIO_PEREN[P9REN] Bits */ +#define P9REN_OFS ( 0) /*!< P9REN Offset */ +#define P9REN_M (0x00ff) /*!< Port 9 Resistor Enable */ +/* DIO_PEREN[P10REN] Bits */ +#define P10REN_OFS ( 8) /*!< P10REN Offset */ +#define P10REN_M (0xff00) /*!< Port 10 Resistor Enable */ +/* DIO_PEDS[P9DS] Bits */ +#define P9DS_OFS ( 0) /*!< P9DS Offset */ +#define P9DS_M (0x00ff) /*!< Port 9 Drive Strength */ +/* DIO_PEDS[P10DS] Bits */ +#define P10DS_OFS ( 8) /*!< P10DS Offset */ +#define P10DS_M (0xff00) /*!< Port 10 Drive Strength */ +/* DIO_PESEL0[P9SEL0] Bits */ +#define P9SEL0_OFS ( 0) /*!< P9SEL0 Offset */ +#define P9SEL0_M (0x00ff) /*!< Port 9 Select 0 */ +/* DIO_PESEL0[P10SEL0] Bits */ +#define P10SEL0_OFS ( 8) /*!< P10SEL0 Offset */ +#define P10SEL0_M (0xff00) /*!< Port 10 Select 0 */ +/* DIO_PESEL1[P9SEL1] Bits */ +#define P9SEL1_OFS ( 0) /*!< P9SEL1 Offset */ +#define P9SEL1_M (0x00ff) /*!< Port 9 Select 1 */ +/* DIO_PESEL1[P10SEL1] Bits */ +#define P10SEL1_OFS ( 8) /*!< P10SEL1 Offset */ +#define P10SEL1_M (0xff00) /*!< Port 10 Select 1 */ +/* DIO_P9IV[P9IV] Bits */ +#define P9IV_OFS ( 0) /*!< P9IV Offset */ +#define P9IV_M (0x001f) /*!< Port 9 interrupt vector value */ +#define P9IV0 (0x0001) /*!< Port 9 interrupt vector value */ +#define P9IV1 (0x0002) /*!< Port 9 interrupt vector value */ +#define P9IV2 (0x0004) /*!< Port 9 interrupt vector value */ +#define P9IV3 (0x0008) /*!< Port 9 interrupt vector value */ +#define P9IV4 (0x0010) /*!< Port 9 interrupt vector value */ +#define P9IV_0 (0x0000) /*!< No interrupt pending */ +#define P9IV_2 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ +#define P9IV_4 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ +#define P9IV_6 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ +#define P9IV_8 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ +#define P9IV_10 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ +#define P9IV_12 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ +#define P9IV_14 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ +#define P9IV_16 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ +#define P9IV__NONE (0x0000) /*!< No interrupt pending */ +#define P9IV__P9IFG0 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ +#define P9IV__P9IFG1 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ +#define P9IV__P9IFG2 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ +#define P9IV__P9IFG3 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ +#define P9IV__P9IFG4 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ +#define P9IV__P9IFG5 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ +#define P9IV__P9IFG6 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ +#define P9IV__P9IFG7 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ +/* DIO_PESELC[P9SELC] Bits */ +#define P9SELC_OFS ( 0) /*!< P9SELC Offset */ +#define P9SELC_M (0x00ff) /*!< Port 9 Complement Select */ +/* DIO_PESELC[P10SELC] Bits */ +#define P10SELC_OFS ( 8) /*!< P10SELC Offset */ +#define P10SELC_M (0xff00) /*!< Port 10 Complement Select */ +/* DIO_PEIES[P9IES] Bits */ +#define P9IES_OFS ( 0) /*!< P9IES Offset */ +#define P9IES_M (0x00ff) /*!< Port 9 Interrupt Edge Select */ +/* DIO_PEIES[P10IES] Bits */ +#define P10IES_OFS ( 8) /*!< P10IES Offset */ +#define P10IES_M (0xff00) /*!< Port 10 Interrupt Edge Select */ +/* DIO_PEIE[P9IE] Bits */ +#define P9IE_OFS ( 0) /*!< P9IE Offset */ +#define P9IE_M (0x00ff) /*!< Port 9 Interrupt Enable */ +/* DIO_PEIE[P10IE] Bits */ +#define P10IE_OFS ( 8) /*!< P10IE Offset */ +#define P10IE_M (0xff00) /*!< Port 10 Interrupt Enable */ +/* DIO_PEIFG[P9IFG] Bits */ +#define P9IFG_OFS ( 0) /*!< P9IFG Offset */ +#define P9IFG_M (0x00ff) /*!< Port 9 Interrupt Flag */ +/* DIO_PEIFG[P10IFG] Bits */ +#define P10IFG_OFS ( 8) /*!< P10IFG Offset */ +#define P10IFG_M (0xff00) /*!< Port 10 Interrupt Flag */ +/* DIO_P10IV[P10IV] Bits */ +#define P10IV_OFS ( 0) /*!< P10IV Offset */ +#define P10IV_M (0x001f) /*!< Port 10 interrupt vector value */ +#define P10IV0 (0x0001) /*!< Port 10 interrupt vector value */ +#define P10IV1 (0x0002) /*!< Port 10 interrupt vector value */ +#define P10IV2 (0x0004) /*!< Port 10 interrupt vector value */ +#define P10IV3 (0x0008) /*!< Port 10 interrupt vector value */ +#define P10IV4 (0x0010) /*!< Port 10 interrupt vector value */ +#define P10IV_0 (0x0000) /*!< No interrupt pending */ +#define P10IV_2 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ +#define P10IV_4 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ +#define P10IV_6 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ +#define P10IV_8 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ +#define P10IV_10 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ +#define P10IV_12 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ +#define P10IV_14 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ +#define P10IV_16 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ +#define P10IV__NONE (0x0000) /*!< No interrupt pending */ +#define P10IV__P10IFG0 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ +#define P10IV__P10IFG1 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ +#define P10IV__P10IFG2 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ +#define P10IV__P10IFG3 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ +#define P10IV__P10IFG4 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ +#define P10IV__P10IFG5 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ +#define P10IV__P10IFG6 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ +#define P10IV__P10IFG7 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ + + +/****************************************************************************** +* EUSCI_A Bits (legacy section) +******************************************************************************/ +/* UCA0CTLW0[UCSWRST] Bits */ +#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ +#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ +/* UCA0CTLW0[UCTXBRK] Bits */ +#define UCTXBRK_OFS EUSCI_A_CTLW0_TXBRK_OFS /*!< UCTXBRK Offset */ +#define UCTXBRK EUSCI_A_CTLW0_TXBRK /*!< Transmit break */ +/* UCA0CTLW0[UCTXADDR] Bits */ +#define UCTXADDR_OFS EUSCI_A_CTLW0_TXADDR_OFS /*!< UCTXADDR Offset */ +#define UCTXADDR EUSCI_A_CTLW0_TXADDR /*!< Transmit address */ +/* UCA0CTLW0[UCDORM] Bits */ +#define UCDORM_OFS EUSCI_A_CTLW0_DORM_OFS /*!< UCDORM Offset */ +#define UCDORM EUSCI_A_CTLW0_DORM /*!< Dormant */ +/* UCA0CTLW0[UCBRKIE] Bits */ +#define UCBRKIE_OFS EUSCI_A_CTLW0_BRKIE_OFS /*!< UCBRKIE Offset */ +#define UCBRKIE EUSCI_A_CTLW0_BRKIE /*!< Receive break character interrupt enable */ +/* UCA0CTLW0[UCRXEIE] Bits */ +#define UCRXEIE_OFS EUSCI_A_CTLW0_RXEIE_OFS /*!< UCRXEIE Offset */ +#define UCRXEIE EUSCI_A_CTLW0_RXEIE /*!< Receive erroneous-character interrupt enable */ +/* UCA0CTLW0[UCSSEL] Bits */ +#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ +#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ +#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ +#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ +#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< UCLK */ +#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ +#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ +#define UCSSEL__UCLK EUSCI_A_CTLW0_SSEL__UCLK /*!< UCLK */ +#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ +#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ +/* UCA0CTLW0[UCSYNC] Bits */ +#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ +#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ +/* UCA0CTLW0[UCMODE] Bits */ +#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ +#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI_A mode */ +#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ +#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ +#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< UART mode */ +#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< Idle-line multiprocessor mode */ +#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< Address-bit multiprocessor mode */ +#define UCMODE_3 EUSCI_A_CTLW0_MODE_3 /*!< UART mode with automatic baud-rate detection */ +/* UCA0CTLW0[UCSPB] Bits */ +#define UCSPB_OFS EUSCI_A_CTLW0_SPB_OFS /*!< UCSPB Offset */ +#define UCSPB EUSCI_A_CTLW0_SPB /*!< Stop bit select */ +/* UCA0CTLW0[UC7BIT] Bits */ +#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ +#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ +/* UCA0CTLW0[UCMSB] Bits */ +#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ +#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ +/* UCA0CTLW0[UCPAR] Bits */ +#define UCPAR_OFS EUSCI_A_CTLW0_PAR_OFS /*!< UCPAR Offset */ +#define UCPAR EUSCI_A_CTLW0_PAR /*!< Parity select */ +/* UCA0CTLW0[UCPEN] Bits */ +#define UCPEN_OFS EUSCI_A_CTLW0_PEN_OFS /*!< UCPEN Offset */ +#define UCPEN EUSCI_A_CTLW0_PEN /*!< Parity enable */ +/* UCA0CTLW0_SPI[UCSWRST] Bits */ +//#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ +//#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ +/* UCA0CTLW0_SPI[UCSTEM] Bits */ +#define UCSTEM_OFS EUSCI_A_CTLW0_STEM_OFS /*!< UCSTEM Offset */ +#define UCSTEM EUSCI_A_CTLW0_STEM /*!< STE mode select in master mode. */ +/* UCA0CTLW0_SPI[UCSSEL] Bits */ +//#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ +//#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ +//#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ +//#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ +//#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< Reserved */ +//#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ +//#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ +//#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ +//#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ +/* UCA0CTLW0_SPI[UCSYNC] Bits */ +//#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ +//#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ +/* UCA0CTLW0_SPI[UCMODE] Bits */ +//#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ +//#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI mode */ +//#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ +//#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ +//#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< 3-pin SPI */ +//#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ +//#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ +/* UCA0CTLW0_SPI[UCMST] Bits */ +#define UCMST_OFS EUSCI_A_CTLW0_MST_OFS /*!< UCMST Offset */ +#define UCMST EUSCI_A_CTLW0_MST /*!< Master mode select */ +/* UCA0CTLW0_SPI[UC7BIT] Bits */ +//#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ +//#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ +/* UCA0CTLW0_SPI[UCMSB] Bits */ +//#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ +//#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ +/* UCA0CTLW0_SPI[UCCKPL] Bits */ +#define UCCKPL_OFS EUSCI_A_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ +#define UCCKPL EUSCI_A_CTLW0_CKPL /*!< Clock polarity select */ +/* UCA0CTLW0_SPI[UCCKPH] Bits */ +#define UCCKPH_OFS EUSCI_A_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ +#define UCCKPH EUSCI_A_CTLW0_CKPH /*!< Clock phase select */ +/* UCA0CTLW1[UCGLIT] Bits */ +#define UCGLIT_OFS EUSCI_A_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ +#define UCGLIT_M EUSCI_A_CTLW1_GLIT_MASK /*!< Deglitch time */ +#define UCGLIT0 EUSCI_A_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ +#define UCGLIT1 EUSCI_A_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ +#define UCGLIT_0 EUSCI_A_CTLW1_GLIT_0 /*!< Approximately 2 ns (equivalent of 1 delay element) */ +#define UCGLIT_1 EUSCI_A_CTLW1_GLIT_1 /*!< Approximately 50 ns */ +#define UCGLIT_2 EUSCI_A_CTLW1_GLIT_2 /*!< Approximately 100 ns */ +#define UCGLIT_3 EUSCI_A_CTLW1_GLIT_3 /*!< Approximately 200 ns */ +/* UCA0MCTLW[UCOS16] Bits */ +#define UCOS16_OFS EUSCI_A_MCTLW_OS16_OFS /*!< UCOS16 Offset */ +#define UCOS16 EUSCI_A_MCTLW_OS16 /*!< Oversampling mode enabled */ +/* UCA0MCTLW[UCBRF] Bits */ +#define UCBRF_OFS EUSCI_A_MCTLW_BRF_OFS /*!< UCBRF Offset */ +#define UCBRF_M EUSCI_A_MCTLW_BRF_MASK /*!< First modulation stage select */ +/* UCA0MCTLW[UCBRS] Bits */ +#define UCBRS_OFS EUSCI_A_MCTLW_BRS_OFS /*!< UCBRS Offset */ +#define UCBRS_M EUSCI_A_MCTLW_BRS_MASK /*!< Second modulation stage select */ +/* UCA0STATW[UCBUSY] Bits */ +#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */ +#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */ +/* UCA0STATW[UCADDR_UCIDLE] Bits */ +#define UCADDR_UCIDLE_OFS EUSCI_A_STATW_ADDR_IDLE_OFS /*!< UCADDR_UCIDLE Offset */ +#define UCADDR_UCIDLE EUSCI_A_STATW_ADDR_IDLE /*!< Address received / Idle line detected */ +/* UCA0STATW[UCRXERR] Bits */ +#define UCRXERR_OFS EUSCI_A_STATW_RXERR_OFS /*!< UCRXERR Offset */ +#define UCRXERR EUSCI_A_STATW_RXERR /*!< Receive error flag */ +/* UCA0STATW[UCBRK] Bits */ +#define UCBRK_OFS EUSCI_A_STATW_BRK_OFS /*!< UCBRK Offset */ +#define UCBRK EUSCI_A_STATW_BRK /*!< Break detect flag */ +/* UCA0STATW[UCPE] Bits */ +#define UCPE_OFS EUSCI_A_STATW_PE_OFS /*!< UCPE Offset */ +#define UCPE EUSCI_A_STATW_PE +/* UCA0STATW[UCOE] Bits */ +#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ +#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ +/* UCA0STATW[UCFE] Bits */ +#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ +#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ +/* UCA0STATW[UCLISTEN] Bits */ +#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ +#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ +/* UCA0STATW_SPI[UCBUSY] Bits */ +//#define UCBUSY_OFS EUSCI_A_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ +//#define UCBUSY EUSCI_A_STATW_SPI_BUSY /*!< eUSCI_A busy */ +/* UCA0STATW_SPI[UCOE] Bits */ +//#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ +//#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ +/* UCA0STATW_SPI[UCFE] Bits */ +//#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ +//#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ +/* UCA0STATW_SPI[UCLISTEN] Bits */ +//#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ +//#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ +/* UCA0RXBUF[UCRXBUF] Bits */ +#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ +#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ +/* UCA0RXBUF_SPI[UCRXBUF] Bits */ +//#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ +//#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ +/* UCA0TXBUF[UCTXBUF] Bits */ +#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ +#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ +/* UCA0TXBUF_SPI[UCTXBUF] Bits */ +//#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ +//#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ +/* UCA0ABCTL[UCABDEN] Bits */ +#define UCABDEN_OFS EUSCI_A_ABCTL_ABDEN_OFS /*!< UCABDEN Offset */ +#define UCABDEN EUSCI_A_ABCTL_ABDEN /*!< Automatic baud-rate detect enable */ +/* UCA0ABCTL[UCBTOE] Bits */ +#define UCBTOE_OFS EUSCI_A_ABCTL_BTOE_OFS /*!< UCBTOE Offset */ +#define UCBTOE EUSCI_A_ABCTL_BTOE /*!< Break time out error */ +/* UCA0ABCTL[UCSTOE] Bits */ +#define UCSTOE_OFS EUSCI_A_ABCTL_STOE_OFS /*!< UCSTOE Offset */ +#define UCSTOE EUSCI_A_ABCTL_STOE /*!< Synch field time out error */ +/* UCA0ABCTL[UCDELIM] Bits */ +#define UCDELIM_OFS EUSCI_A_ABCTL_DELIM_OFS /*!< UCDELIM Offset */ +#define UCDELIM_M EUSCI_A_ABCTL_DELIM_MASK /*!< Break/synch delimiter length */ +#define UCDELIM0 EUSCI_A_ABCTL_DELIM0 /*!< UCDELIM Bit 0 */ +#define UCDELIM1 EUSCI_A_ABCTL_DELIM1 /*!< UCDELIM Bit 1 */ +#define UCDELIM_0 EUSCI_A_ABCTL_DELIM_0 /*!< 1 bit time */ +#define UCDELIM_1 EUSCI_A_ABCTL_DELIM_1 /*!< 2 bit times */ +#define UCDELIM_2 EUSCI_A_ABCTL_DELIM_2 /*!< 3 bit times */ +#define UCDELIM_3 EUSCI_A_ABCTL_DELIM_3 /*!< 4 bit times */ +/* UCA0IRCTL[UCIREN] Bits */ +#define UCIREN_OFS EUSCI_A_IRCTL_IREN_OFS /*!< UCIREN Offset */ +#define UCIREN EUSCI_A_IRCTL_IREN /*!< IrDA encoder/decoder enable */ +/* UCA0IRCTL[UCIRTXCLK] Bits */ +#define UCIRTXCLK_OFS EUSCI_A_IRCTL_IRTXCLK_OFS /*!< UCIRTXCLK Offset */ +#define UCIRTXCLK EUSCI_A_IRCTL_IRTXCLK /*!< IrDA transmit pulse clock select */ +/* UCA0IRCTL[UCIRTXPL] Bits */ +#define UCIRTXPL_OFS EUSCI_A_IRCTL_IRTXPL_OFS /*!< UCIRTXPL Offset */ +#define UCIRTXPL_M EUSCI_A_IRCTL_IRTXPL_MASK /*!< Transmit pulse length */ +/* UCA0IRCTL[UCIRRXFE] Bits */ +#define UCIRRXFE_OFS EUSCI_A_IRCTL_IRRXFE_OFS /*!< UCIRRXFE Offset */ +#define UCIRRXFE EUSCI_A_IRCTL_IRRXFE /*!< IrDA receive filter enabled */ +/* UCA0IRCTL[UCIRRXPL] Bits */ +#define UCIRRXPL_OFS EUSCI_A_IRCTL_IRRXPL_OFS /*!< UCIRRXPL Offset */ +#define UCIRRXPL EUSCI_A_IRCTL_IRRXPL /*!< IrDA receive input UCAxRXD polarity */ +/* UCA0IRCTL[UCIRRXFL] Bits */ +#define UCIRRXFL_OFS EUSCI_A_IRCTL_IRRXFL_OFS /*!< UCIRRXFL Offset */ +#define UCIRRXFL_M EUSCI_A_IRCTL_IRRXFL_MASK /*!< Receive filter length */ +/* UCA0IE[UCRXIE] Bits */ +#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ +#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ +/* UCA0IE[UCTXIE] Bits */ +#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ +#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ +/* UCA0IE[UCSTTIE] Bits */ +#define UCSTTIE_OFS EUSCI_A_IE_STTIE_OFS /*!< UCSTTIE Offset */ +#define UCSTTIE EUSCI_A_IE_STTIE /*!< Start bit interrupt enable */ +/* UCA0IE[UCTXCPTIE] Bits */ +#define UCTXCPTIE_OFS EUSCI_A_IE_TXCPTIE_OFS /*!< UCTXCPTIE Offset */ +#define UCTXCPTIE EUSCI_A_IE_TXCPTIE /*!< Transmit complete interrupt enable */ +/* UCA0IE_SPI[UCRXIE] Bits */ +//#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ +//#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ +/* UCA0IE_SPI[UCTXIE] Bits */ +//#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ +//#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ +/* UCA0IFG[UCRXIFG] Bits */ +#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ +#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ +/* UCA0IFG[UCTXIFG] Bits */ +#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ +#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ +/* UCA0IFG[UCSTTIFG] Bits */ +#define UCSTTIFG_OFS EUSCI_A_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ +#define UCSTTIFG EUSCI_A_IFG_STTIFG /*!< Start bit interrupt flag */ +/* UCA0IFG[UCTXCPTIFG] Bits */ +#define UCTXCPTIFG_OFS EUSCI_A_IFG_TXCPTIFG_OFS /*!< UCTXCPTIFG Offset */ +#define UCTXCPTIFG EUSCI_A_IFG_TXCPTIFG /*!< Transmit ready interrupt enable */ +/* UCA0IFG_SPI[UCRXIFG] Bits */ +//#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ +//#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ +/* UCA0IFG_SPI[UCTXIFG] Bits */ +//#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ +//#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ + +/****************************************************************************** +* EUSCI_B Bits (legacy section) +******************************************************************************/ +/* UCB0CTLW0[UCSWRST] Bits */ +//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ +//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ +/* UCB0CTLW0[UCTXSTT] Bits */ +#define UCTXSTT_OFS EUSCI_B_CTLW0_TXSTT_OFS /*!< UCTXSTT Offset */ +#define UCTXSTT EUSCI_B_CTLW0_TXSTT /*!< Transmit START condition in master mode */ +/* UCB0CTLW0[UCTXSTP] Bits */ +#define UCTXSTP_OFS EUSCI_B_CTLW0_TXSTP_OFS /*!< UCTXSTP Offset */ +#define UCTXSTP EUSCI_B_CTLW0_TXSTP /*!< Transmit STOP condition in master mode */ +/* UCB0CTLW0[UCTXNACK] Bits */ +#define UCTXNACK_OFS EUSCI_B_CTLW0_TXNACK_OFS /*!< UCTXNACK Offset */ +#define UCTXNACK EUSCI_B_CTLW0_TXNACK /*!< Transmit a NACK */ +/* UCB0CTLW0[UCTR] Bits */ +#define UCTR_OFS EUSCI_B_CTLW0_TR_OFS /*!< UCTR Offset */ +#define UCTR EUSCI_B_CTLW0_TR /*!< Transmitter/receiver */ +/* UCB0CTLW0[UCTXACK] Bits */ +#define UCTXACK_OFS EUSCI_B_CTLW0_TXACK_OFS /*!< UCTXACK Offset */ +#define UCTXACK EUSCI_B_CTLW0_TXACK /*!< Transmit ACK condition in slave mode */ +/* UCB0CTLW0[UCSSEL] Bits */ +//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ +//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ +//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ +//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ +//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< UCLKI */ +//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ +//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ +#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ +#define UCSSEL__UCLKI EUSCI_B_CTLW0_SSEL__UCLKI /*!< UCLKI */ +//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ +//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ +/* UCB0CTLW0[UCSYNC] Bits */ +//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ +//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ +/* UCB0CTLW0[UCMODE] Bits */ +//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ +//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI_B mode */ +//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ +//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ +//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ +//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI (master or slave enabled if STE = 1) */ +//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI (master or slave enabled if STE = 0) */ +//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ +/* UCB0CTLW0[UCMST] Bits */ +//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ +//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ +/* UCB0CTLW0[UCMM] Bits */ +#define UCMM_OFS EUSCI_B_CTLW0_MM_OFS /*!< UCMM Offset */ +#define UCMM EUSCI_B_CTLW0_MM /*!< Multi-master environment select */ +/* UCB0CTLW0[UCSLA10] Bits */ +#define UCSLA10_OFS EUSCI_B_CTLW0_SLA10_OFS /*!< UCSLA10 Offset */ +#define UCSLA10 EUSCI_B_CTLW0_SLA10 /*!< Slave addressing mode select */ +/* UCB0CTLW0[UCA10] Bits */ +#define UCA10_OFS EUSCI_B_CTLW0_A10_OFS /*!< UCA10 Offset */ +#define UCA10 EUSCI_B_CTLW0_A10 /*!< Own addressing mode select */ +/* UCB0CTLW0_SPI[UCSWRST] Bits */ +//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ +//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ +/* UCB0CTLW0_SPI[UCSTEM] Bits */ +//#define UCSTEM_OFS EUSCI_B_CTLW0_STEM_OFS /*!< UCSTEM Offset */ +//#define UCSTEM EUSCI_B_CTLW0_STEM /*!< STE mode select in master mode. */ +/* UCB0CTLW0_SPI[UCSSEL] Bits */ +//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ +//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ +//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ +//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ +//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< Reserved */ +//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ +//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ +//#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ +//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ +//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ +/* UCB0CTLW0_SPI[UCSYNC] Bits */ +//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ +//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ +/* UCB0CTLW0_SPI[UCMODE] Bits */ +//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ +//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI mode */ +//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ +//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ +//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ +//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ +//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ +//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ +/* UCB0CTLW0_SPI[UCMST] Bits */ +//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ +//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ +/* UCB0CTLW0_SPI[UC7BIT] Bits */ +//#define UC7BIT_OFS EUSCI_B_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ +//#define UC7BIT EUSCI_B_CTLW0_SEVENBIT /*!< Character length */ +/* UCB0CTLW0_SPI[UCMSB] Bits */ +//#define UCMSB_OFS EUSCI_B_CTLW0_MSB_OFS /*!< UCMSB Offset */ +//#define UCMSB EUSCI_B_CTLW0_MSB /*!< MSB first select */ +/* UCB0CTLW0_SPI[UCCKPL] Bits */ +//#define UCCKPL_OFS EUSCI_B_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ +//#define UCCKPL EUSCI_B_CTLW0_CKPL /*!< Clock polarity select */ +/* UCB0CTLW0_SPI[UCCKPH] Bits */ +//#define UCCKPH_OFS EUSCI_B_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ +//#define UCCKPH EUSCI_B_CTLW0_CKPH /*!< Clock phase select */ +/* UCB0CTLW1[UCGLIT] Bits */ +//#define UCGLIT_OFS EUSCI_B_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ +//#define UCGLIT_M EUSCI_B_CTLW1_GLIT_MASK /*!< Deglitch time */ +//#define UCGLIT0 EUSCI_B_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ +//#define UCGLIT1 EUSCI_B_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ +//#define UCGLIT_0 EUSCI_B_CTLW1_GLIT_0 /*!< 50 ns */ +//#define UCGLIT_1 EUSCI_B_CTLW1_GLIT_1 /*!< 25 ns */ +//#define UCGLIT_2 EUSCI_B_CTLW1_GLIT_2 /*!< 12.5 ns */ +//#define UCGLIT_3 EUSCI_B_CTLW1_GLIT_3 /*!< 6.25 ns */ +/* UCB0CTLW1[UCASTP] Bits */ +#define UCASTP_OFS EUSCI_B_CTLW1_ASTP_OFS /*!< UCASTP Offset */ +#define UCASTP_M EUSCI_B_CTLW1_ASTP_MASK /*!< Automatic STOP condition generation */ +#define UCASTP0 EUSCI_B_CTLW1_ASTP0 /*!< UCASTP Bit 0 */ +#define UCASTP1 EUSCI_B_CTLW1_ASTP1 /*!< UCASTP Bit 1 */ +#define UCASTP_0 EUSCI_B_CTLW1_ASTP_0 /*!< No automatic STOP generation. The STOP condition is generated after the user */ + /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ +#define UCASTP_1 EUSCI_B_CTLW1_ASTP_1 /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ + /* UCBxTBCNT */ +#define UCASTP_2 EUSCI_B_CTLW1_ASTP_2 /*!< A STOP condition is generated automatically after the byte counter value */ + /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ + /* threshold */ +/* UCB0CTLW1[UCSWACK] Bits */ +#define UCSWACK_OFS EUSCI_B_CTLW1_SWACK_OFS /*!< UCSWACK Offset */ +#define UCSWACK EUSCI_B_CTLW1_SWACK /*!< SW or HW ACK control */ +/* UCB0CTLW1[UCSTPNACK] Bits */ +#define UCSTPNACK_OFS EUSCI_B_CTLW1_STPNACK_OFS /*!< UCSTPNACK Offset */ +#define UCSTPNACK EUSCI_B_CTLW1_STPNACK /*!< ACK all master bytes */ +/* UCB0CTLW1[UCCLTO] Bits */ +#define UCCLTO_OFS EUSCI_B_CTLW1_CLTO_OFS /*!< UCCLTO Offset */ +#define UCCLTO_M EUSCI_B_CTLW1_CLTO_MASK /*!< Clock low timeout select */ +#define UCCLTO0 EUSCI_B_CTLW1_CLTO0 /*!< UCCLTO Bit 0 */ +#define UCCLTO1 EUSCI_B_CTLW1_CLTO1 /*!< UCCLTO Bit 1 */ +#define UCCLTO_0 EUSCI_B_CTLW1_CLTO_0 /*!< Disable clock low timeout counter */ +#define UCCLTO_1 EUSCI_B_CTLW1_CLTO_1 /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ +#define UCCLTO_2 EUSCI_B_CTLW1_CLTO_2 /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ +#define UCCLTO_3 EUSCI_B_CTLW1_CLTO_3 /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ +/* UCB0CTLW1[UCETXINT] Bits */ +#define UCETXINT_OFS EUSCI_B_CTLW1_ETXINT_OFS /*!< UCETXINT Offset */ +#define UCETXINT EUSCI_B_CTLW1_ETXINT /*!< Early UCTXIFG0 */ +/* UCB0STATW[UCBBUSY] Bits */ +#define UCBBUSY_OFS EUSCI_B_STATW_BBUSY_OFS /*!< UCBBUSY Offset */ +#define UCBBUSY EUSCI_B_STATW_BBUSY /*!< Bus busy */ +/* UCB0STATW[UCGC] Bits */ +#define UCGC_OFS EUSCI_B_STATW_GC_OFS /*!< UCGC Offset */ +#define UCGC EUSCI_B_STATW_GC /*!< General call address received */ +/* UCB0STATW[UCSCLLOW] Bits */ +#define UCSCLLOW_OFS EUSCI_B_STATW_SCLLOW_OFS /*!< UCSCLLOW Offset */ +#define UCSCLLOW EUSCI_B_STATW_SCLLOW /*!< SCL low */ +/* UCB0STATW[UCBCNT] Bits */ +#define UCBCNT_OFS EUSCI_B_STATW_BCNT_OFS /*!< UCBCNT Offset */ +#define UCBCNT_M EUSCI_B_STATW_BCNT_MASK /*!< Hardware byte counter value */ +/* UCB0STATW_SPI[UCBUSY] Bits */ +//#define UCBUSY_OFS EUSCI_B_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ +//#define UCBUSY EUSCI_B_STATW_SPI_BUSY /*!< eUSCI_B busy */ +/* UCB0STATW_SPI[UCOE] Bits */ +//#define UCOE_OFS EUSCI_B_STATW_OE_OFS /*!< UCOE Offset */ +//#define UCOE EUSCI_B_STATW_OE /*!< Overrun error flag */ +/* UCB0STATW_SPI[UCFE] Bits */ +//#define UCFE_OFS EUSCI_B_STATW_FE_OFS /*!< UCFE Offset */ +//#define UCFE EUSCI_B_STATW_FE /*!< Framing error flag */ +/* UCB0STATW_SPI[UCLISTEN] Bits */ +//#define UCLISTEN_OFS EUSCI_B_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ +//#define UCLISTEN EUSCI_B_STATW_LISTEN /*!< Listen enable */ +/* UCB0TBCNT[UCTBCNT] Bits */ +#define UCTBCNT_OFS EUSCI_B_TBCNT_TBCNT_OFS /*!< UCTBCNT Offset */ +#define UCTBCNT_M EUSCI_B_TBCNT_TBCNT_MASK /*!< Byte counter threshold value */ +/* UCB0RXBUF[UCRXBUF] Bits */ +//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ +//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ +/* UCB0RXBUF_SPI[UCRXBUF] Bits */ +//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ +//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ +/* UCB0TXBUF[UCTXBUF] Bits */ +//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ +//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ +/* UCB0TXBUF_SPI[UCTXBUF] Bits */ +//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ +//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ +/* UCB0I2COA0[I2COA0] Bits */ +#define I2COA0_OFS EUSCI_B_I2COA0_I2COA0_OFS /*!< I2COA0 Offset */ +#define I2COA0_M EUSCI_B_I2COA0_I2COA0_MASK /*!< I2C own address */ +/* UCB0I2COA0[UCOAEN] Bits */ +#define UCOAEN_OFS EUSCI_B_I2COA0_OAEN_OFS /*!< UCOAEN Offset */ +#define UCOAEN EUSCI_B_I2COA0_OAEN /*!< Own Address enable register */ +/* UCB0I2COA0[UCGCEN] Bits */ +#define UCGCEN_OFS EUSCI_B_I2COA0_GCEN_OFS /*!< UCGCEN Offset */ +#define UCGCEN EUSCI_B_I2COA0_GCEN /*!< General call response enable */ +/* UCB0I2COA1[I2COA1] Bits */ +#define I2COA1_OFS EUSCI_B_I2COA1_I2COA1_OFS /*!< I2COA1 Offset */ +#define I2COA1_M EUSCI_B_I2COA1_I2COA1_MASK /*!< I2C own address */ +/* UCB0I2COA1[UCOAEN] Bits */ +//#define UCOAEN_OFS EUSCI_B_I2COA1_OAEN_OFS /*!< UCOAEN Offset */ +//#define UCOAEN EUSCI_B_I2COA1_OAEN /*!< Own Address enable register */ +/* UCB0I2COA2[I2COA2] Bits */ +#define I2COA2_OFS EUSCI_B_I2COA2_I2COA2_OFS /*!< I2COA2 Offset */ +#define I2COA2_M EUSCI_B_I2COA2_I2COA2_MASK /*!< I2C own address */ +/* UCB0I2COA2[UCOAEN] Bits */ +//#define UCOAEN_OFS EUSCI_B_I2COA2_OAEN_OFS /*!< UCOAEN Offset */ +//#define UCOAEN EUSCI_B_I2COA2_OAEN /*!< Own Address enable register */ +/* UCB0I2COA3[I2COA3] Bits */ +#define I2COA3_OFS EUSCI_B_I2COA3_I2COA3_OFS /*!< I2COA3 Offset */ +#define I2COA3_M EUSCI_B_I2COA3_I2COA3_MASK /*!< I2C own address */ +/* UCB0I2COA3[UCOAEN] Bits */ +//#define UCOAEN_OFS EUSCI_B_I2COA3_OAEN_OFS /*!< UCOAEN Offset */ +//#define UCOAEN EUSCI_B_I2COA3_OAEN /*!< Own Address enable register */ +/* UCB0ADDRX[ADDRX] Bits */ +#define ADDRX_OFS EUSCI_B_ADDRX_ADDRX_OFS /*!< ADDRX Offset */ +#define ADDRX_M EUSCI_B_ADDRX_ADDRX_MASK /*!< Received Address Register */ +#define ADDRX0 EUSCI_B_ADDRX_ADDRX0 /*!< ADDRX Bit 0 */ +#define ADDRX1 EUSCI_B_ADDRX_ADDRX1 /*!< ADDRX Bit 1 */ +#define ADDRX2 EUSCI_B_ADDRX_ADDRX2 /*!< ADDRX Bit 2 */ +#define ADDRX3 EUSCI_B_ADDRX_ADDRX3 /*!< ADDRX Bit 3 */ +#define ADDRX4 EUSCI_B_ADDRX_ADDRX4 /*!< ADDRX Bit 4 */ +#define ADDRX5 EUSCI_B_ADDRX_ADDRX5 /*!< ADDRX Bit 5 */ +#define ADDRX6 EUSCI_B_ADDRX_ADDRX6 /*!< ADDRX Bit 6 */ +#define ADDRX7 EUSCI_B_ADDRX_ADDRX7 /*!< ADDRX Bit 7 */ +#define ADDRX8 EUSCI_B_ADDRX_ADDRX8 /*!< ADDRX Bit 8 */ +#define ADDRX9 EUSCI_B_ADDRX_ADDRX9 /*!< ADDRX Bit 9 */ +/* UCB0ADDMASK[ADDMASK] Bits */ +#define ADDMASK_OFS EUSCI_B_ADDMASK_ADDMASK_OFS /*!< ADDMASK Offset */ +#define ADDMASK_M EUSCI_B_ADDMASK_ADDMASK_MASK +/* UCB0I2CSA[I2CSA] Bits */ +#define I2CSA_OFS EUSCI_B_I2CSA_I2CSA_OFS /*!< I2CSA Offset */ +#define I2CSA_M EUSCI_B_I2CSA_I2CSA_MASK /*!< I2C slave address */ +/* UCB0IE[UCRXIE0] Bits */ +#define UCRXIE0_OFS EUSCI_B_IE_RXIE0_OFS /*!< UCRXIE0 Offset */ +#define UCRXIE0 EUSCI_B_IE_RXIE0 /*!< Receive interrupt enable 0 */ +/* UCB0IE[UCTXIE0] Bits */ +#define UCTXIE0_OFS EUSCI_B_IE_TXIE0_OFS /*!< UCTXIE0 Offset */ +#define UCTXIE0 EUSCI_B_IE_TXIE0 /*!< Transmit interrupt enable 0 */ +/* UCB0IE[UCSTTIE] Bits */ +//#define UCSTTIE_OFS EUSCI_B_IE_STTIE_OFS /*!< UCSTTIE Offset */ +//#define UCSTTIE EUSCI_B_IE_STTIE /*!< START condition interrupt enable */ +/* UCB0IE[UCSTPIE] Bits */ +#define UCSTPIE_OFS EUSCI_B_IE_STPIE_OFS /*!< UCSTPIE Offset */ +#define UCSTPIE EUSCI_B_IE_STPIE /*!< STOP condition interrupt enable */ +/* UCB0IE[UCALIE] Bits */ +#define UCALIE_OFS EUSCI_B_IE_ALIE_OFS /*!< UCALIE Offset */ +#define UCALIE EUSCI_B_IE_ALIE /*!< Arbitration lost interrupt enable */ +/* UCB0IE[UCNACKIE] Bits */ +#define UCNACKIE_OFS EUSCI_B_IE_NACKIE_OFS /*!< UCNACKIE Offset */ +#define UCNACKIE EUSCI_B_IE_NACKIE /*!< Not-acknowledge interrupt enable */ +/* UCB0IE[UCBCNTIE] Bits */ +#define UCBCNTIE_OFS EUSCI_B_IE_BCNTIE_OFS /*!< UCBCNTIE Offset */ +#define UCBCNTIE EUSCI_B_IE_BCNTIE /*!< Byte counter interrupt enable */ +/* UCB0IE[UCCLTOIE] Bits */ +#define UCCLTOIE_OFS EUSCI_B_IE_CLTOIE_OFS /*!< UCCLTOIE Offset */ +#define UCCLTOIE EUSCI_B_IE_CLTOIE /*!< Clock low timeout interrupt enable */ +/* UCB0IE[UCRXIE1] Bits */ +#define UCRXIE1_OFS EUSCI_B_IE_RXIE1_OFS /*!< UCRXIE1 Offset */ +#define UCRXIE1 EUSCI_B_IE_RXIE1 /*!< Receive interrupt enable 1 */ +/* UCB0IE[UCTXIE1] Bits */ +#define UCTXIE1_OFS EUSCI_B_IE_TXIE1_OFS /*!< UCTXIE1 Offset */ +#define UCTXIE1 EUSCI_B_IE_TXIE1 /*!< Transmit interrupt enable 1 */ +/* UCB0IE[UCRXIE2] Bits */ +#define UCRXIE2_OFS EUSCI_B_IE_RXIE2_OFS /*!< UCRXIE2 Offset */ +#define UCRXIE2 EUSCI_B_IE_RXIE2 /*!< Receive interrupt enable 2 */ +/* UCB0IE[UCTXIE2] Bits */ +#define UCTXIE2_OFS EUSCI_B_IE_TXIE2_OFS /*!< UCTXIE2 Offset */ +#define UCTXIE2 EUSCI_B_IE_TXIE2 /*!< Transmit interrupt enable 2 */ +/* UCB0IE[UCRXIE3] Bits */ +#define UCRXIE3_OFS EUSCI_B_IE_RXIE3_OFS /*!< UCRXIE3 Offset */ +#define UCRXIE3 EUSCI_B_IE_RXIE3 /*!< Receive interrupt enable 3 */ +/* UCB0IE[UCTXIE3] Bits */ +#define UCTXIE3_OFS EUSCI_B_IE_TXIE3_OFS /*!< UCTXIE3 Offset */ +#define UCTXIE3 EUSCI_B_IE_TXIE3 /*!< Transmit interrupt enable 3 */ +/* UCB0IE[UCBIT9IE] Bits */ +#define UCBIT9IE_OFS EUSCI_B_IE_BIT9IE_OFS /*!< UCBIT9IE Offset */ +#define UCBIT9IE EUSCI_B_IE_BIT9IE /*!< Bit position 9 interrupt enable */ +/* UCB0IE_SPI[UCRXIE] Bits */ +//#define UCRXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Offset */ +//#define UCRXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ +/* UCB0IE_SPI[UCTXIE] Bits */ +//#define UCTXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Offset */ +//#define UCTXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ +/* UCB0IFG[UCRXIFG0] Bits */ +#define UCRXIFG0_OFS EUSCI_B_IFG_RXIFG0_OFS /*!< UCRXIFG0 Offset */ +#define UCRXIFG0 EUSCI_B_IFG_RXIFG0 /*!< eUSCI_B receive interrupt flag 0 */ +/* UCB0IFG[UCTXIFG0] Bits */ +#define UCTXIFG0_OFS EUSCI_B_IFG_TXIFG0_OFS /*!< UCTXIFG0 Offset */ +#define UCTXIFG0 EUSCI_B_IFG_TXIFG0 /*!< eUSCI_B transmit interrupt flag 0 */ +/* UCB0IFG[UCSTTIFG] Bits */ +//#define UCSTTIFG_OFS EUSCI_B_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ +//#define UCSTTIFG EUSCI_B_IFG_STTIFG /*!< START condition interrupt flag */ +/* UCB0IFG[UCSTPIFG] Bits */ +#define UCSTPIFG_OFS EUSCI_B_IFG_STPIFG_OFS /*!< UCSTPIFG Offset */ +#define UCSTPIFG EUSCI_B_IFG_STPIFG /*!< STOP condition interrupt flag */ +/* UCB0IFG[UCALIFG] Bits */ +#define UCALIFG_OFS EUSCI_B_IFG_ALIFG_OFS /*!< UCALIFG Offset */ +#define UCALIFG EUSCI_B_IFG_ALIFG /*!< Arbitration lost interrupt flag */ +/* UCB0IFG[UCNACKIFG] Bits */ +#define UCNACKIFG_OFS EUSCI_B_IFG_NACKIFG_OFS /*!< UCNACKIFG Offset */ +#define UCNACKIFG EUSCI_B_IFG_NACKIFG /*!< Not-acknowledge received interrupt flag */ +/* UCB0IFG[UCBCNTIFG] Bits */ +#define UCBCNTIFG_OFS EUSCI_B_IFG_BCNTIFG_OFS /*!< UCBCNTIFG Offset */ +#define UCBCNTIFG EUSCI_B_IFG_BCNTIFG /*!< Byte counter interrupt flag */ +/* UCB0IFG[UCCLTOIFG] Bits */ +#define UCCLTOIFG_OFS EUSCI_B_IFG_CLTOIFG_OFS /*!< UCCLTOIFG Offset */ +#define UCCLTOIFG EUSCI_B_IFG_CLTOIFG /*!< Clock low timeout interrupt flag */ +/* UCB0IFG[UCRXIFG1] Bits */ +#define UCRXIFG1_OFS EUSCI_B_IFG_RXIFG1_OFS /*!< UCRXIFG1 Offset */ +#define UCRXIFG1 EUSCI_B_IFG_RXIFG1 /*!< eUSCI_B receive interrupt flag 1 */ +/* UCB0IFG[UCTXIFG1] Bits */ +#define UCTXIFG1_OFS EUSCI_B_IFG_TXIFG1_OFS /*!< UCTXIFG1 Offset */ +#define UCTXIFG1 EUSCI_B_IFG_TXIFG1 /*!< eUSCI_B transmit interrupt flag 1 */ +/* UCB0IFG[UCRXIFG2] Bits */ +#define UCRXIFG2_OFS EUSCI_B_IFG_RXIFG2_OFS /*!< UCRXIFG2 Offset */ +#define UCRXIFG2 EUSCI_B_IFG_RXIFG2 /*!< eUSCI_B receive interrupt flag 2 */ +/* UCB0IFG[UCTXIFG2] Bits */ +#define UCTXIFG2_OFS EUSCI_B_IFG_TXIFG2_OFS /*!< UCTXIFG2 Offset */ +#define UCTXIFG2 EUSCI_B_IFG_TXIFG2 /*!< eUSCI_B transmit interrupt flag 2 */ +/* UCB0IFG[UCRXIFG3] Bits */ +#define UCRXIFG3_OFS EUSCI_B_IFG_RXIFG3_OFS /*!< UCRXIFG3 Offset */ +#define UCRXIFG3 EUSCI_B_IFG_RXIFG3 /*!< eUSCI_B receive interrupt flag 3 */ +/* UCB0IFG[UCTXIFG3] Bits */ +#define UCTXIFG3_OFS EUSCI_B_IFG_TXIFG3_OFS /*!< UCTXIFG3 Offset */ +#define UCTXIFG3 EUSCI_B_IFG_TXIFG3 /*!< eUSCI_B transmit interrupt flag 3 */ +/* UCB0IFG[UCBIT9IFG] Bits */ +#define UCBIT9IFG_OFS EUSCI_B_IFG_BIT9IFG_OFS /*!< UCBIT9IFG Offset */ +#define UCBIT9IFG EUSCI_B_IFG_BIT9IFG /*!< Bit position 9 interrupt flag */ +/* UCB0IFG_SPI[UCRXIFG] Bits */ +//#define UCRXIFG_OFS EUSCI_B_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ +//#define UCRXIFG EUSCI_B_IFG_RXIFG /*!< Receive interrupt flag */ +/* UCB0IFG_SPI[UCTXIFG] Bits */ +//#define UCTXIFG_OFS EUSCI_B_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ +//#define UCTXIFG EUSCI_B_IFG_TXIFG /*!< Transmit interrupt flag */ + +/****************************************************************************** +* PMAP Bits (legacy section) +******************************************************************************/ +/* PMAPCTL[PMAPLOCKED] Bits */ +#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ +#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ +/* PMAPCTL[PMAPRECFG] Bits */ +#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ +#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ +/* Pre-defined bitfield values */ +/* PMAP_PMAPCTL[PMAPLOCKED] Bits */ +#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ +#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ +/* PMAP_PMAPCTL[PMAPRECFG] Bits */ +#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ +#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ + +#define PM_NONE PMAP_NONE +#define PM_UCA0CLK PMAP_UCA0CLK +#define PM_UCA0RXD PMAP_UCA0RXD +#define PM_UCA0SOMI PMAP_UCA0SOMI +#define PM_UCA0TXD PMAP_UCA0TXD +#define PM_UCA0SIMO PMAP_UCA0SIMO +#define PM_UCB0CLK PMAP_UCB0CLK +#define PM_UCB0SDA PMAP_UCB0SDA +#define PM_UCB0SIMO PMAP_UCB0SIMO +#define PM_UCB0SCL PMAP_UCB0SCL +#define PM_UCB0SOMI PMAP_UCB0SOMI +#define PM_UCA1STE PMAP_UCA1STE +#define PM_UCA1CLK PMAP_UCA1CLK +#define PM_UCA1RXD PMAP_UCA1RXD +#define PM_UCA1SOMI PMAP_UCA1SOMI +#define PM_UCA1TXD PMAP_UCA1TXD +#define PM_UCA1SIMO PMAP_UCA1SIMO +#define PM_UCA2STE PMAP_UCA2STE +#define PM_UCA2CLK PMAP_UCA2CLK +#define PM_UCA2RXD PMAP_UCA2RXD +#define PM_UCA2SOMI PMAP_UCA2SOMI +#define PM_UCA2TXD PMAP_UCA2TXD +#define PM_UCA2SIMO PMAP_UCA2SIMO +#define PM_UCB2STE PMAP_UCB2STE +#define PM_UCB2CLK PMAP_UCB2CLK +#define PM_UCB2SDA PMAP_UCB2SDA +#define PM_UCB2SIMO PMAP_UCB2SIMO +#define PM_UCB2SCL PMAP_UCB2SCL +#define PM_UCB2SOMI PMAP_UCB2SOMI +#define PM_TA0CCR0A PMAP_TA0CCR0A +#define PM_TA0CCR1A PMAP_TA0CCR1A +#define PM_TA0CCR2A PMAP_TA0CCR2A +#define PM_TA0CCR3A PMAP_TA0CCR3A +#define PM_TA0CCR4A PMAP_TA0CCR4A +#define PM_TA1CCR1A PMAP_TA1CCR1A +#define PM_TA1CCR2A PMAP_TA1CCR2A +#define PM_TA1CCR3A PMAP_TA1CCR3A +#define PM_TA1CCR4A PMAP_TA1CCR4A +#define PM_TA0CLK PMAP_TA0CLK +#define PM_CE0OUT PMAP_CE0OUT +#define PM_TA1CLK PMAP_TA1CLK +#define PM_CE1OUT PMAP_CE1OUT +#define PM_DMAE0 PMAP_DMAE0 +#define PM_SMCLK PMAP_SMCLK +#define PM_ANALOG PMAP_ANALOG + +#define PMAPKEY PMAP_KEYID_VAL /*!< Port Mapping Key */ +#define PMAPPWD PMAP_KEYID_VAL /*!< Legacy Definition: Mapping Key register */ +#define PMAPPW PMAP_KEYID_VAL /*!< Legacy Definition: Port Mapping Password */ + + +/****************************************************************************** +* REF_A Bits (legacy section) +******************************************************************************/ +/* REFCTL0[REFON] Bits */ +#define REFON_OFS REF_A_CTL0_ON_OFS /*!< REFON Offset */ +#define REFON REF_A_CTL0_ON /*!< Reference enable */ +/* REFCTL0[REFOUT] Bits */ +#define REFOUT_OFS REF_A_CTL0_OUT_OFS /*!< REFOUT Offset */ +#define REFOUT REF_A_CTL0_OUT /*!< Reference output buffer */ +/* REFCTL0[REFTCOFF] Bits */ +#define REFTCOFF_OFS REF_A_CTL0_TCOFF_OFS /*!< REFTCOFF Offset */ +#define REFTCOFF REF_A_CTL0_TCOFF /*!< Temperature sensor disabled */ +/* REFCTL0[REFVSEL] Bits */ +#define REFVSEL_OFS REF_A_CTL0_VSEL_OFS /*!< REFVSEL Offset */ +#define REFVSEL_M REF_A_CTL0_VSEL_MASK /*!< Reference voltage level select */ +#define REFVSEL0 REF_A_CTL0_VSEL0 /*!< REFVSEL Bit 0 */ +#define REFVSEL1 REF_A_CTL0_VSEL1 /*!< REFVSEL Bit 1 */ +#define REFVSEL_0 REF_A_CTL0_VSEL_0 /*!< 1.2 V available when reference requested or REFON = 1 */ +#define REFVSEL_1 REF_A_CTL0_VSEL_1 /*!< 1.45 V available when reference requested or REFON = 1 */ +#define REFVSEL_3 REF_A_CTL0_VSEL_3 /*!< 2.5 V available when reference requested or REFON = 1 */ +/* REFCTL0[REFGENOT] Bits */ +#define REFGENOT_OFS REF_A_CTL0_GENOT_OFS /*!< REFGENOT Offset */ +#define REFGENOT REF_A_CTL0_GENOT /*!< Reference generator one-time trigger */ +/* REFCTL0[REFBGOT] Bits */ +#define REFBGOT_OFS REF_A_CTL0_BGOT_OFS /*!< REFBGOT Offset */ +#define REFBGOT REF_A_CTL0_BGOT /*!< Bandgap and bandgap buffer one-time trigger */ +/* REFCTL0[REFGENACT] Bits */ +#define REFGENACT_OFS REF_A_CTL0_GENACT_OFS /*!< REFGENACT Offset */ +#define REFGENACT REF_A_CTL0_GENACT /*!< Reference generator active */ +/* REFCTL0[REFBGACT] Bits */ +#define REFBGACT_OFS REF_A_CTL0_BGACT_OFS /*!< REFBGACT Offset */ +#define REFBGACT REF_A_CTL0_BGACT /*!< Reference bandgap active */ +/* REFCTL0[REFGENBUSY] Bits */ +#define REFGENBUSY_OFS REF_A_CTL0_GENBUSY_OFS /*!< REFGENBUSY Offset */ +#define REFGENBUSY REF_A_CTL0_GENBUSY /*!< Reference generator busy */ +/* REFCTL0[BGMODE] Bits */ +#define BGMODE_OFS REF_A_CTL0_BGMODE_OFS /*!< BGMODE Offset */ +#define BGMODE REF_A_CTL0_BGMODE /*!< Bandgap mode */ +/* REFCTL0[REFGENRDY] Bits */ +#define REFGENRDY_OFS REF_A_CTL0_GENRDY_OFS /*!< REFGENRDY Offset */ +#define REFGENRDY REF_A_CTL0_GENRDY /*!< Variable reference voltage ready status */ +/* REFCTL0[REFBGRDY] Bits */ +#define REFBGRDY_OFS REF_A_CTL0_BGRDY_OFS /*!< REFBGRDY Offset */ +#define REFBGRDY REF_A_CTL0_BGRDY /*!< Buffered bandgap voltage ready status */ + +/****************************************************************************** +* RTC_C Bits (legacy section) +******************************************************************************/ +/* RTCCTL0[RTCRDYIFG] Bits */ +#define RTCRDYIFG_OFS RTC_C_CTL0_RDYIFG_OFS /*!< RTCRDYIFG Offset */ +#define RTCRDYIFG RTC_C_CTL0_RDYIFG /*!< Real-time clock ready interrupt flag */ +/* RTCCTL0[RTCAIFG] Bits */ +#define RTCAIFG_OFS RTC_C_CTL0_AIFG_OFS /*!< RTCAIFG Offset */ +#define RTCAIFG RTC_C_CTL0_AIFG /*!< Real-time clock alarm interrupt flag */ +/* RTCCTL0[RTCTEVIFG] Bits */ +#define RTCTEVIFG_OFS RTC_C_CTL0_TEVIFG_OFS /*!< RTCTEVIFG Offset */ +#define RTCTEVIFG RTC_C_CTL0_TEVIFG /*!< Real-time clock time event interrupt flag */ +/* RTCCTL0[RTCOFIFG] Bits */ +#define RTCOFIFG_OFS RTC_C_CTL0_OFIFG_OFS /*!< RTCOFIFG Offset */ +#define RTCOFIFG RTC_C_CTL0_OFIFG /*!< 32-kHz crystal oscillator fault interrupt flag */ +/* RTCCTL0[RTCRDYIE] Bits */ +#define RTCRDYIE_OFS RTC_C_CTL0_RDYIE_OFS /*!< RTCRDYIE Offset */ +#define RTCRDYIE RTC_C_CTL0_RDYIE /*!< Real-time clock ready interrupt enable */ +/* RTCCTL0[RTCAIE] Bits */ +#define RTCAIE_OFS RTC_C_CTL0_AIE_OFS /*!< RTCAIE Offset */ +#define RTCAIE RTC_C_CTL0_AIE /*!< Real-time clock alarm interrupt enable */ +/* RTCCTL0[RTCTEVIE] Bits */ +#define RTCTEVIE_OFS RTC_C_CTL0_TEVIE_OFS /*!< RTCTEVIE Offset */ +#define RTCTEVIE RTC_C_CTL0_TEVIE /*!< Real-time clock time event interrupt enable */ +/* RTCCTL0[RTCOFIE] Bits */ +#define RTCOFIE_OFS RTC_C_CTL0_OFIE_OFS /*!< RTCOFIE Offset */ +#define RTCOFIE RTC_C_CTL0_OFIE /*!< 32-kHz crystal oscillator fault interrupt enable */ +/* RTCCTL0[RTCKEY] Bits */ +#define RTCKEY_OFS RTC_C_CTL0_KEY_OFS /*!< RTCKEY Offset */ +#define RTCKEY_M RTC_C_CTL0_KEY_MASK /*!< Real-time clock key */ +/* RTCCTL13[RTCTEV] Bits */ +#define RTCTEV_OFS RTC_C_CTL13_TEV_OFS /*!< RTCTEV Offset */ +#define RTCTEV_M RTC_C_CTL13_TEV_MASK /*!< Real-time clock time event */ +#define RTCTEV0 RTC_C_CTL13_TEV0 /*!< RTCTEV Bit 0 */ +#define RTCTEV1 RTC_C_CTL13_TEV1 /*!< RTCTEV Bit 1 */ +#define RTCTEV_0 RTC_C_CTL13_TEV_0 /*!< Minute changed */ +#define RTCTEV_1 RTC_C_CTL13_TEV_1 /*!< Hour changed */ +#define RTCTEV_2 RTC_C_CTL13_TEV_2 /*!< Every day at midnight (00:00) */ +#define RTCTEV_3 RTC_C_CTL13_TEV_3 /*!< Every day at noon (12:00) */ +/* RTCCTL13[RTCSSEL] Bits */ +#define RTCSSEL_OFS RTC_C_CTL13_SSEL_OFS /*!< RTCSSEL Offset */ +#define RTCSSEL_M RTC_C_CTL13_SSEL_MASK /*!< Real-time clock source select */ +#define RTCSSEL0 RTC_C_CTL13_SSEL0 /*!< RTCSSEL Bit 0 */ +#define RTCSSEL1 RTC_C_CTL13_SSEL1 /*!< RTCSSEL Bit 1 */ +#define RTCSSEL_0 RTC_C_CTL13_SSEL_0 /*!< BCLK */ +#define RTCSSEL__BCLK RTC_C_CTL13_SSEL__BCLK /*!< BCLK */ +/* RTCCTL13[RTCRDY] Bits */ +#define RTCRDY_OFS RTC_C_CTL13_RDY_OFS /*!< RTCRDY Offset */ +#define RTCRDY RTC_C_CTL13_RDY /*!< Real-time clock ready */ +/* RTCCTL13[RTCMODE] Bits */ +#define RTCMODE_OFS RTC_C_CTL13_MODE_OFS /*!< RTCMODE Offset */ +#define RTCMODE RTC_C_CTL13_MODE +/* RTCCTL13[RTCHOLD] Bits */ +#define RTCHOLD_OFS RTC_C_CTL13_HOLD_OFS /*!< RTCHOLD Offset */ +#define RTCHOLD RTC_C_CTL13_HOLD /*!< Real-time clock hold */ +/* RTCCTL13[RTCBCD] Bits */ +#define RTCBCD_OFS RTC_C_CTL13_BCD_OFS /*!< RTCBCD Offset */ +#define RTCBCD RTC_C_CTL13_BCD /*!< Real-time clock BCD select */ +/* RTCCTL13[RTCCALF] Bits */ +#define RTCCALF_OFS RTC_C_CTL13_CALF_OFS /*!< RTCCALF Offset */ +#define RTCCALF_M RTC_C_CTL13_CALF_MASK /*!< Real-time clock calibration frequency */ +#define RTCCALF0 RTC_C_CTL13_CALF0 /*!< RTCCALF Bit 0 */ +#define RTCCALF1 RTC_C_CTL13_CALF1 /*!< RTCCALF Bit 1 */ +#define RTCCALF_0 RTC_C_CTL13_CALF_0 /*!< No frequency output to RTCCLK pin */ +#define RTCCALF_1 RTC_C_CTL13_CALF_1 /*!< 512 Hz */ +#define RTCCALF_2 RTC_C_CTL13_CALF_2 /*!< 256 Hz */ +#define RTCCALF_3 RTC_C_CTL13_CALF_3 /*!< 1 Hz */ +#define RTCCALF__NONE RTC_C_CTL13_CALF__NONE /*!< No frequency output to RTCCLK pin */ +#define RTCCALF__512 RTC_C_CTL13_CALF__512 /*!< 512 Hz */ +#define RTCCALF__256 RTC_C_CTL13_CALF__256 /*!< 256 Hz */ +#define RTCCALF__1 RTC_C_CTL13_CALF__1 /*!< 1 Hz */ +/* RTCOCAL[RTCOCAL] Bits */ +#define RTCOCAL_OFS RTC_C_OCAL_OCAL_OFS /*!< RTCOCAL Offset */ +#define RTCOCAL_M RTC_C_OCAL_OCAL_MASK /*!< Real-time clock offset error calibration */ +/* RTCOCAL[RTCOCALS] Bits */ +#define RTCOCALS_OFS RTC_C_OCAL_OCALS_OFS /*!< RTCOCALS Offset */ +#define RTCOCALS RTC_C_OCAL_OCALS /*!< Real-time clock offset error calibration sign */ +/* RTCTCMP[RTCTCMP] Bits */ +#define RTCTCMP_OFS RTC_C_TCMP_TCMPX_OFS /*!< RTCTCMP Offset */ +#define RTCTCMP_M RTC_C_TCMP_TCMPX_MASK /*!< Real-time clock temperature compensation */ +/* RTCTCMP[RTCTCOK] Bits */ +#define RTCTCOK_OFS RTC_C_TCMP_TCOK_OFS /*!< RTCTCOK Offset */ +#define RTCTCOK RTC_C_TCMP_TCOK /*!< Real-time clock temperature compensation write OK */ +/* RTCTCMP[RTCTCRDY] Bits */ +#define RTCTCRDY_OFS RTC_C_TCMP_TCRDY_OFS /*!< RTCTCRDY Offset */ +#define RTCTCRDY RTC_C_TCMP_TCRDY /*!< Real-time clock temperature compensation ready */ +/* RTCTCMP[RTCTCMPS] Bits */ +#define RTCTCMPS_OFS RTC_C_TCMP_TCMPS_OFS /*!< RTCTCMPS Offset */ +#define RTCTCMPS RTC_C_TCMP_TCMPS /*!< Real-time clock temperature compensation sign */ +/* RTCPS0CTL[RT0PSIFG] Bits */ +#define RT0PSIFG_OFS RTC_C_PS0CTL_RT0PSIFG_OFS /*!< RT0PSIFG Offset */ +#define RT0PSIFG RTC_C_PS0CTL_RT0PSIFG /*!< Prescale timer 0 interrupt flag */ +/* RTCPS0CTL[RT0PSIE] Bits */ +#define RT0PSIE_OFS RTC_C_PS0CTL_RT0PSIE_OFS /*!< RT0PSIE Offset */ +#define RT0PSIE RTC_C_PS0CTL_RT0PSIE /*!< Prescale timer 0 interrupt enable */ +/* RTCPS0CTL[RT0IP] Bits */ +#define RT0IP_OFS RTC_C_PS0CTL_RT0IP_OFS /*!< RT0IP Offset */ +#define RT0IP_M RTC_C_PS0CTL_RT0IP_MASK /*!< Prescale timer 0 interrupt interval */ +#define RT0IP0 RTC_C_PS0CTL_RT0IP0 /*!< RT0IP Bit 0 */ +#define RT0IP1 RTC_C_PS0CTL_RT0IP1 /*!< RT0IP Bit 1 */ +#define RT0IP2 RTC_C_PS0CTL_RT0IP2 /*!< RT0IP Bit 2 */ +#define RT0IP_0 RTC_C_PS0CTL_RT0IP_0 /*!< Divide by 2 */ +#define RT0IP_1 RTC_C_PS0CTL_RT0IP_1 /*!< Divide by 4 */ +#define RT0IP_2 RTC_C_PS0CTL_RT0IP_2 /*!< Divide by 8 */ +#define RT0IP_3 RTC_C_PS0CTL_RT0IP_3 /*!< Divide by 16 */ +#define RT0IP_4 RTC_C_PS0CTL_RT0IP_4 /*!< Divide by 32 */ +#define RT0IP_5 RTC_C_PS0CTL_RT0IP_5 /*!< Divide by 64 */ +#define RT0IP_6 RTC_C_PS0CTL_RT0IP_6 /*!< Divide by 128 */ +#define RT0IP_7 RTC_C_PS0CTL_RT0IP_7 /*!< Divide by 256 */ +#define RT0IP__2 RTC_C_PS0CTL_RT0IP__2 /*!< Divide by 2 */ +#define RT0IP__4 RTC_C_PS0CTL_RT0IP__4 /*!< Divide by 4 */ +#define RT0IP__8 RTC_C_PS0CTL_RT0IP__8 /*!< Divide by 8 */ +#define RT0IP__16 RTC_C_PS0CTL_RT0IP__16 /*!< Divide by 16 */ +#define RT0IP__32 RTC_C_PS0CTL_RT0IP__32 /*!< Divide by 32 */ +#define RT0IP__64 RTC_C_PS0CTL_RT0IP__64 /*!< Divide by 64 */ +#define RT0IP__128 RTC_C_PS0CTL_RT0IP__128 /*!< Divide by 128 */ +#define RT0IP__256 RTC_C_PS0CTL_RT0IP__256 /*!< Divide by 256 */ +/* RTCPS1CTL[RT1PSIFG] Bits */ +#define RT1PSIFG_OFS RTC_C_PS1CTL_RT1PSIFG_OFS /*!< RT1PSIFG Offset */ +#define RT1PSIFG RTC_C_PS1CTL_RT1PSIFG /*!< Prescale timer 1 interrupt flag */ +/* RTCPS1CTL[RT1PSIE] Bits */ +#define RT1PSIE_OFS RTC_C_PS1CTL_RT1PSIE_OFS /*!< RT1PSIE Offset */ +#define RT1PSIE RTC_C_PS1CTL_RT1PSIE /*!< Prescale timer 1 interrupt enable */ +/* RTCPS1CTL[RT1IP] Bits */ +#define RT1IP_OFS RTC_C_PS1CTL_RT1IP_OFS /*!< RT1IP Offset */ +#define RT1IP_M RTC_C_PS1CTL_RT1IP_MASK /*!< Prescale timer 1 interrupt interval */ +#define RT1IP0 RTC_C_PS1CTL_RT1IP0 /*!< RT1IP Bit 0 */ +#define RT1IP1 RTC_C_PS1CTL_RT1IP1 /*!< RT1IP Bit 1 */ +#define RT1IP2 RTC_C_PS1CTL_RT1IP2 /*!< RT1IP Bit 2 */ +#define RT1IP_0 RTC_C_PS1CTL_RT1IP_0 /*!< Divide by 2 */ +#define RT1IP_1 RTC_C_PS1CTL_RT1IP_1 /*!< Divide by 4 */ +#define RT1IP_2 RTC_C_PS1CTL_RT1IP_2 /*!< Divide by 8 */ +#define RT1IP_3 RTC_C_PS1CTL_RT1IP_3 /*!< Divide by 16 */ +#define RT1IP_4 RTC_C_PS1CTL_RT1IP_4 /*!< Divide by 32 */ +#define RT1IP_5 RTC_C_PS1CTL_RT1IP_5 /*!< Divide by 64 */ +#define RT1IP_6 RTC_C_PS1CTL_RT1IP_6 /*!< Divide by 128 */ +#define RT1IP_7 RTC_C_PS1CTL_RT1IP_7 /*!< Divide by 256 */ +#define RT1IP__2 RTC_C_PS1CTL_RT1IP__2 /*!< Divide by 2 */ +#define RT1IP__4 RTC_C_PS1CTL_RT1IP__4 /*!< Divide by 4 */ +#define RT1IP__8 RTC_C_PS1CTL_RT1IP__8 /*!< Divide by 8 */ +#define RT1IP__16 RTC_C_PS1CTL_RT1IP__16 /*!< Divide by 16 */ +#define RT1IP__32 RTC_C_PS1CTL_RT1IP__32 /*!< Divide by 32 */ +#define RT1IP__64 RTC_C_PS1CTL_RT1IP__64 /*!< Divide by 64 */ +#define RT1IP__128 RTC_C_PS1CTL_RT1IP__128 /*!< Divide by 128 */ +#define RT1IP__256 RTC_C_PS1CTL_RT1IP__256 /*!< Divide by 256 */ +/* RTCPS[RT0PS] Bits */ +#define RT0PS_OFS RTC_C_PS_RT0PS_OFS /*!< RT0PS Offset */ +#define RT0PS_M RTC_C_PS_RT0PS_MASK /*!< Prescale timer 0 counter value */ +/* RTCPS[RT1PS] Bits */ +#define RT1PS_OFS RTC_C_PS_RT1PS_OFS /*!< RT1PS Offset */ +#define RT1PS_M RTC_C_PS_RT1PS_MASK /*!< Prescale timer 1 counter value */ +/* RTCTIM0[SECONDS] Bits */ +#define SECONDS_OFS RTC_C_TIM0_SEC_OFS /*!< Seconds Offset */ +#define SECONDS_M RTC_C_TIM0_SEC_MASK /*!< Seconds (0 to 59) */ +/* RTCTIM0[MINUTES] Bits */ +#define MINUTES_OFS RTC_C_TIM0_MIN_OFS /*!< Minutes Offset */ +#define MINUTES_M RTC_C_TIM0_MIN_MASK /*!< Minutes (0 to 59) */ +/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */ +#define SECONDSLOWDIGIT_OFS RTC_C_TIM0_SEC_LD_OFS /*!< SecondsLowDigit Offset */ +#define SECONDSLOWDIGIT_M RTC_C_TIM0_SEC_LD_MASK /*!< Seconds low digit (0 to 9) */ +/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */ +#define SECONDSHIGHDIGIT_OFS RTC_C_TIM0_SEC_HD_OFS /*!< SecondsHighDigit Offset */ +#define SECONDSHIGHDIGIT_M RTC_C_TIM0_SEC_HD_MASK /*!< Seconds high digit (0 to 5) */ +/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */ +#define MINUTESLOWDIGIT_OFS RTC_C_TIM0_MIN_LD_OFS /*!< MinutesLowDigit Offset */ +#define MINUTESLOWDIGIT_M RTC_C_TIM0_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ +/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */ +#define MINUTESHIGHDIGIT_OFS RTC_C_TIM0_MIN_HD_OFS /*!< MinutesHighDigit Offset */ +#define MINUTESHIGHDIGIT_M RTC_C_TIM0_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ +/* RTCTIM1[HOURS] Bits */ +#define HOURS_OFS RTC_C_TIM1_HOUR_OFS /*!< Hours Offset */ +#define HOURS_M RTC_C_TIM1_HOUR_MASK /*!< Hours (0 to 23) */ +/* RTCTIM1[DAYOFWEEK] Bits */ +#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ +#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ +/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */ +#define HOURSLOWDIGIT_OFS RTC_C_TIM1_HOUR_LD_OFS /*!< HoursLowDigit Offset */ +#define HOURSLOWDIGIT_M RTC_C_TIM1_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ +/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */ +#define HOURSHIGHDIGIT_OFS RTC_C_TIM1_HOUR_HD_OFS /*!< HoursHighDigit Offset */ +#define HOURSHIGHDIGIT_M RTC_C_TIM1_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ +/* RTCTIM1_BCD[DAYOFWEEK] Bits */ +//#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ +//#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ +/* RTCDATE[DAY] Bits */ +#define DAY_OFS RTC_C_DATE_DAY_OFS /*!< Day Offset */ +#define DAY_M RTC_C_DATE_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ +/* RTCDATE[MONTH] Bits */ +#define MONTH_OFS RTC_C_DATE_MON_OFS /*!< Month Offset */ +#define MONTH_M RTC_C_DATE_MON_MASK /*!< Month (1 to 12) */ +/* RTCDATE_BCD[DAYLOWDIGIT] Bits */ +#define DAYLOWDIGIT_OFS RTC_C_DATE_DAY_LD_OFS /*!< DayLowDigit Offset */ +#define DAYLOWDIGIT_M RTC_C_DATE_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ +/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */ +#define DAYHIGHDIGIT_OFS RTC_C_DATE_DAY_HD_OFS /*!< DayHighDigit Offset */ +#define DAYHIGHDIGIT_M RTC_C_DATE_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ +/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */ +#define MONTHLOWDIGIT_OFS RTC_C_DATE_MON_LD_OFS /*!< MonthLowDigit Offset */ +#define MONTHLOWDIGIT_M RTC_C_DATE_MON_LD_MASK /*!< Month low digit (0 to 9) */ +/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */ +#define MONTHHIGHDIGIT_OFS RTC_C_DATE_MON_HD_OFS /*!< MonthHighDigit Offset */ +#define MONTHHIGHDIGIT RTC_C_DATE_MON_HD /*!< Month high digit (0 or 1) */ +/* RTCYEAR[YEARLOWBYTE] Bits */ +#define YEARLOWBYTE_OFS RTC_C_YEAR_YEAR_LB_OFS /*!< YearLowByte Offset */ +#define YEARLOWBYTE_M RTC_C_YEAR_YEAR_LB_MASK /*!< Year low byte. Valid values for Year are 0 to 4095. */ +/* RTCYEAR[YEARHIGHBYTE] Bits */ +#define YEARHIGHBYTE_OFS RTC_C_YEAR_YEAR_HB_OFS /*!< YearHighByte Offset */ +#define YEARHIGHBYTE_M RTC_C_YEAR_YEAR_HB_MASK /*!< Year high byte. Valid values for Year are 0 to 4095. */ +/* RTCYEAR_BCD[YEAR] Bits */ +#define YEAR_OFS RTC_C_YEAR_YEAR_OFS /*!< Year Offset */ +#define YEAR_M RTC_C_YEAR_YEAR_MASK /*!< Year lowest digit (0 to 9) */ +/* RTCYEAR_BCD[DECADE] Bits */ +#define DECADE_OFS RTC_C_YEAR_DEC_OFS /*!< Decade Offset */ +#define DECADE_M RTC_C_YEAR_DEC_MASK /*!< Decade (0 to 9) */ +/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */ +#define CENTURYLOWDIGIT_OFS RTC_C_YEAR_CENT_LD_OFS /*!< CenturyLowDigit Offset */ +#define CENTURYLOWDIGIT_M RTC_C_YEAR_CENT_LD_MASK /*!< Century low digit (0 to 9) */ +/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */ +#define CENTURYHIGHDIGIT_OFS RTC_C_YEAR_CENT_HD_OFS /*!< CenturyHighDigit Offset */ +#define CENTURYHIGHDIGIT_M RTC_C_YEAR_CENT_HD_MASK /*!< Century high digit (0 to 4) */ +/* RTCAMINHR[MINUTES] Bits */ +//#define MINUTES_OFS RTC_C_AMINHR_MIN_OFS /*!< Minutes Offset */ +//#define MINUTES_M RTC_C_AMINHR_MIN_MASK /*!< Minutes (0 to 59) */ +/* RTCAMINHR[MINAE] Bits */ +#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ +#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ +/* RTCAMINHR[HOURS] Bits */ +//#define HOURS_OFS RTC_C_AMINHR_HOUR_OFS /*!< Hours Offset */ +//#define HOURS_M RTC_C_AMINHR_HOUR_MASK /*!< Hours (0 to 23) */ +/* RTCAMINHR[HOURAE] Bits */ +#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ +#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ +/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */ +//#define MINUTESLOWDIGIT_OFS RTC_C_AMINHR_MIN_LD_OFS /*!< MinutesLowDigit Offset */ +//#define MINUTESLOWDIGIT_M RTC_C_AMINHR_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ +/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */ +//#define MINUTESHIGHDIGIT_OFS RTC_C_AMINHR_MIN_HD_OFS /*!< MinutesHighDigit Offset */ +//#define MINUTESHIGHDIGIT_M RTC_C_AMINHR_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ +/* RTCAMINHR_BCD[MINAE] Bits */ +//#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ +//#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ +/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */ +//#define HOURSLOWDIGIT_OFS RTC_C_AMINHR_HOUR_LD_OFS /*!< HoursLowDigit Offset */ +//#define HOURSLOWDIGIT_M RTC_C_AMINHR_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ +/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */ +//#define HOURSHIGHDIGIT_OFS RTC_C_AMINHR_HOUR_HD_OFS /*!< HoursHighDigit Offset */ +//#define HOURSHIGHDIGIT_M RTC_C_AMINHR_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ +/* RTCAMINHR_BCD[HOURAE] Bits */ +//#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ +//#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ +/* RTCADOWDAY[DAYOFWEEK] Bits */ +//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ +//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ +/* RTCADOWDAY[DOWAE] Bits */ +#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ +#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ +/* RTCADOWDAY[DAYOFMONTH] Bits */ +#define DAYOFMONTH_OFS RTC_C_ADOWDAY_DAY_OFS /*!< DayofMonth Offset */ +#define DAYOFMONTH_M RTC_C_ADOWDAY_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ +/* RTCADOWDAY[DAYAE] Bits */ +#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ +#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ +/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */ +//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ +//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ +/* RTCADOWDAY_BCD[DOWAE] Bits */ +//#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ +//#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ +/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */ +//#define DAYLOWDIGIT_OFS RTC_C_ADOWDAY_DAY_LD_OFS /*!< DayLowDigit Offset */ +//#define DAYLOWDIGIT_M RTC_C_ADOWDAY_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ +/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */ +//#define DAYHIGHDIGIT_OFS RTC_C_ADOWDAY_DAY_HD_OFS /*!< DayHighDigit Offset */ +//#define DAYHIGHDIGIT_M RTC_C_ADOWDAY_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ +/* RTCADOWDAY_BCD[DAYAE] Bits */ +//#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ +//#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ +/* Pre-defined bitfield values */ +#define RTCKEY RTC_C_KEY /*!< RTC_C Key Value for RTC_C write access */ +#define RTCKEY_H RTC_C_KEY_H /*!< RTC_C Key Value for RTC_C write access */ +#define RTCKEY_VAL RTC_C_KEY_VAL /*!< RTC_C Key Value for RTC_C write access */ + + +/****************************************************************************** +* TIMER_A Bits (legacy section) +******************************************************************************/ +/* TA0CTL[TAIFG] Bits */ +#define TAIFG_OFS TIMER_A_CTL_IFG_OFS /*!< TAIFG Offset */ +#define TAIFG TIMER_A_CTL_IFG /*!< TimerA interrupt flag */ +/* TA0CTL[TAIE] Bits */ +#define TAIE_OFS TIMER_A_CTL_IE_OFS /*!< TAIE Offset */ +#define TAIE TIMER_A_CTL_IE /*!< TimerA interrupt enable */ +/* TA0CTL[TACLR] Bits */ +#define TACLR_OFS TIMER_A_CTL_CLR_OFS /*!< TACLR Offset */ +#define TACLR TIMER_A_CTL_CLR /*!< TimerA clear */ +/* TA0CTL[MC] Bits */ +#define MC_OFS TIMER_A_CTL_MC_OFS /*!< MC Offset */ +#define MC_M TIMER_A_CTL_MC_MASK /*!< Mode control */ +#define MC0 TIMER_A_CTL_MC0 /*!< MC Bit 0 */ +#define MC1 TIMER_A_CTL_MC1 /*!< MC Bit 1 */ +#define MC_0 TIMER_A_CTL_MC_0 /*!< Stop mode: Timer is halted */ +#define MC_1 TIMER_A_CTL_MC_1 /*!< Up mode: Timer counts up to TAxCCR0 */ +#define MC_2 TIMER_A_CTL_MC_2 /*!< Continuous mode: Timer counts up to 0FFFFh */ +#define MC_3 TIMER_A_CTL_MC_3 /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +#define MC__STOP TIMER_A_CTL_MC__STOP /*!< Stop mode: Timer is halted */ +#define MC__UP TIMER_A_CTL_MC__UP /*!< Up mode: Timer counts up to TAxCCR0 */ +#define MC__CONTINUOUS TIMER_A_CTL_MC__CONTINUOUS /*!< Continuous mode: Timer counts up to 0FFFFh */ +#define MC__UPDOWN TIMER_A_CTL_MC__UPDOWN /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +/* TA0CTL[ID] Bits */ +#define ID_OFS TIMER_A_CTL_ID_OFS /*!< ID Offset */ +#define ID_M TIMER_A_CTL_ID_MASK /*!< Input divider */ +#define ID0 TIMER_A_CTL_ID0 /*!< ID Bit 0 */ +#define ID1 TIMER_A_CTL_ID1 /*!< ID Bit 1 */ +#define ID_0 TIMER_A_CTL_ID_0 /*!< /1 */ +#define ID_1 TIMER_A_CTL_ID_1 /*!< /2 */ +#define ID_2 TIMER_A_CTL_ID_2 /*!< /4 */ +#define ID_3 TIMER_A_CTL_ID_3 /*!< /8 */ +#define ID__1 TIMER_A_CTL_ID__1 /*!< /1 */ +#define ID__2 TIMER_A_CTL_ID__2 /*!< /2 */ +#define ID__4 TIMER_A_CTL_ID__4 /*!< /4 */ +#define ID__8 TIMER_A_CTL_ID__8 /*!< /8 */ +/* TA0CTL[TASSEL] Bits */ +#define TASSEL_OFS TIMER_A_CTL_SSEL_OFS /*!< TASSEL Offset */ +#define TASSEL_M TIMER_A_CTL_SSEL_MASK /*!< TimerA clock source select */ +#define TASSEL0 TIMER_A_CTL_SSEL0 /*!< TASSEL Bit 0 */ +#define TASSEL1 TIMER_A_CTL_SSEL1 /*!< TASSEL Bit 1 */ +#define TASSEL_0 TIMER_A_CTL_TASSEL_0 /*!< TAxCLK */ +#define TASSEL_1 TIMER_A_CTL_TASSEL_1 /*!< ACLK */ +#define TASSEL_2 TIMER_A_CTL_TASSEL_2 /*!< SMCLK */ +#define TASSEL_3 TIMER_A_CTL_TASSEL_3 /*!< INCLK */ +#define TASSEL__TACLK TIMER_A_CTL_SSEL__TACLK /*!< TAxCLK */ +#define TASSEL__ACLK TIMER_A_CTL_SSEL__ACLK /*!< ACLK */ +#define TASSEL__SMCLK TIMER_A_CTL_SSEL__SMCLK /*!< SMCLK */ +#define TASSEL__INCLK TIMER_A_CTL_SSEL__INCLK /*!< INCLK */ +/* TA0CCTLn[CCIFG] Bits */ +#define CCIFG_OFS TIMER_A_CCTLN_CCIFG_OFS /*!< CCIFG Offset */ +#define CCIFG TIMER_A_CCTLN_CCIFG /*!< Capture/compare interrupt flag */ +/* TA0CCTLn[COV] Bits */ +#define COV_OFS TIMER_A_CCTLN_COV_OFS /*!< COV Offset */ +#define COV TIMER_A_CCTLN_COV /*!< Capture overflow */ +/* TA0CCTLn[OUT] Bits */ +#define OUT_OFS TIMER_A_CCTLN_OUT_OFS /*!< OUT Offset */ +//#define OUT TIMER_A_CCTLN_OUT /*!< Output */ +/* TA0CCTLn[CCI] Bits */ +#define CCI_OFS TIMER_A_CCTLN_CCI_OFS /*!< CCI Offset */ +#define CCI TIMER_A_CCTLN_CCI /*!< Capture/compare input */ +/* TA0CCTLn[CCIE] Bits */ +#define CCIE_OFS TIMER_A_CCTLN_CCIE_OFS /*!< CCIE Offset */ +#define CCIE TIMER_A_CCTLN_CCIE /*!< Capture/compare interrupt enable */ +/* TA0CCTLn[OUTMOD] Bits */ +#define OUTMOD_OFS TIMER_A_CCTLN_OUTMOD_OFS /*!< OUTMOD Offset */ +#define OUTMOD_M TIMER_A_CCTLN_OUTMOD_MASK /*!< Output mode */ +#define OUTMOD0 TIMER_A_CCTLN_OUTMOD0 /*!< OUTMOD Bit 0 */ +#define OUTMOD1 TIMER_A_CCTLN_OUTMOD1 /*!< OUTMOD Bit 1 */ +#define OUTMOD2 TIMER_A_CCTLN_OUTMOD2 /*!< OUTMOD Bit 2 */ +#define OUTMOD_0 TIMER_A_CCTLN_OUTMOD_0 /*!< OUT bit value */ +#define OUTMOD_1 TIMER_A_CCTLN_OUTMOD_1 /*!< Set */ +#define OUTMOD_2 TIMER_A_CCTLN_OUTMOD_2 /*!< Toggle/reset */ +#define OUTMOD_3 TIMER_A_CCTLN_OUTMOD_3 /*!< Set/reset */ +#define OUTMOD_4 TIMER_A_CCTLN_OUTMOD_4 /*!< Toggle */ +#define OUTMOD_5 TIMER_A_CCTLN_OUTMOD_5 /*!< Reset */ +#define OUTMOD_6 TIMER_A_CCTLN_OUTMOD_6 /*!< Toggle/set */ +#define OUTMOD_7 TIMER_A_CCTLN_OUTMOD_7 /*!< Reset/set */ +/* TA0CCTLn[CAP] Bits */ +#define CAP_OFS TIMER_A_CCTLN_CAP_OFS /*!< CAP Offset */ +#define CAP TIMER_A_CCTLN_CAP /*!< Capture mode */ +/* TA0CCTLn[SCCI] Bits */ +#define SCCI_OFS TIMER_A_CCTLN_SCCI_OFS /*!< SCCI Offset */ +#define SCCI TIMER_A_CCTLN_SCCI /*!< Synchronized capture/compare input */ +/* TA0CCTLn[SCS] Bits */ +#define SCS_OFS TIMER_A_CCTLN_SCS_OFS /*!< SCS Offset */ +#define SCS TIMER_A_CCTLN_SCS /*!< Synchronize capture source */ +/* TA0CCTLn[CCIS] Bits */ +#define CCIS_OFS TIMER_A_CCTLN_CCIS_OFS /*!< CCIS Offset */ +#define CCIS_M TIMER_A_CCTLN_CCIS_MASK /*!< Capture/compare input select */ +#define CCIS0 TIMER_A_CCTLN_CCIS0 /*!< CCIS Bit 0 */ +#define CCIS1 TIMER_A_CCTLN_CCIS1 /*!< CCIS Bit 1 */ +#define CCIS_0 TIMER_A_CCTLN_CCIS_0 /*!< CCIxA */ +#define CCIS_1 TIMER_A_CCTLN_CCIS_1 /*!< CCIxB */ +#define CCIS_2 TIMER_A_CCTLN_CCIS_2 /*!< GND */ +#define CCIS_3 TIMER_A_CCTLN_CCIS_3 /*!< VCC */ +#define CCIS__CCIA TIMER_A_CCTLN_CCIS__CCIA /*!< CCIxA */ +#define CCIS__CCIB TIMER_A_CCTLN_CCIS__CCIB /*!< CCIxB */ +#define CCIS__GND TIMER_A_CCTLN_CCIS__GND /*!< GND */ +#define CCIS__VCC TIMER_A_CCTLN_CCIS__VCC /*!< VCC */ +/* TA0CCTLn[CM] Bits */ +#define CM_OFS TIMER_A_CCTLN_CM_OFS /*!< CM Offset */ +#define CM_M TIMER_A_CCTLN_CM_MASK /*!< Capture mode */ +#define CM0 TIMER_A_CCTLN_CM0 /*!< CM Bit 0 */ +#define CM1 TIMER_A_CCTLN_CM1 /*!< CM Bit 1 */ +#define CM_0 TIMER_A_CCTLN_CM_0 /*!< No capture */ +#define CM_1 TIMER_A_CCTLN_CM_1 /*!< Capture on rising edge */ +#define CM_2 TIMER_A_CCTLN_CM_2 /*!< Capture on falling edge */ +#define CM_3 TIMER_A_CCTLN_CM_3 /*!< Capture on both rising and falling edges */ +#define CM__NONE TIMER_A_CCTLN_CM__NONE /*!< No capture */ +#define CM__RISING TIMER_A_CCTLN_CM__RISING /*!< Capture on rising edge */ +#define CM__FALLING TIMER_A_CCTLN_CM__FALLING /*!< Capture on falling edge */ +#define CM__BOTH TIMER_A_CCTLN_CM__BOTH /*!< Capture on both rising and falling edges */ +/* TA0EX0[TAIDEX] Bits */ +#define TAIDEX_OFS TIMER_A_EX0_IDEX_OFS /*!< TAIDEX Offset */ +#define TAIDEX_M TIMER_A_EX0_IDEX_MASK /*!< Input divider expansion */ +#define TAIDEX0 TIMER_A_EX0_IDEX0 /*!< TAIDEX Bit 0 */ +#define TAIDEX1 TIMER_A_EX0_IDEX1 /*!< TAIDEX Bit 1 */ +#define TAIDEX2 TIMER_A_EX0_IDEX2 /*!< TAIDEX Bit 2 */ +#define TAIDEX_0 TIMER_A_EX0_TAIDEX_0 /*!< Divide by 1 */ +#define TAIDEX_1 TIMER_A_EX0_TAIDEX_1 /*!< Divide by 2 */ +#define TAIDEX_2 TIMER_A_EX0_TAIDEX_2 /*!< Divide by 3 */ +#define TAIDEX_3 TIMER_A_EX0_TAIDEX_3 /*!< Divide by 4 */ +#define TAIDEX_4 TIMER_A_EX0_TAIDEX_4 /*!< Divide by 5 */ +#define TAIDEX_5 TIMER_A_EX0_TAIDEX_5 /*!< Divide by 6 */ +#define TAIDEX_6 TIMER_A_EX0_TAIDEX_6 /*!< Divide by 7 */ +#define TAIDEX_7 TIMER_A_EX0_TAIDEX_7 /*!< Divide by 8 */ +#define TAIDEX__1 TIMER_A_EX0_IDEX__1 /*!< Divide by 1 */ +#define TAIDEX__2 TIMER_A_EX0_IDEX__2 /*!< Divide by 2 */ +#define TAIDEX__3 TIMER_A_EX0_IDEX__3 /*!< Divide by 3 */ +#define TAIDEX__4 TIMER_A_EX0_IDEX__4 /*!< Divide by 4 */ +#define TAIDEX__5 TIMER_A_EX0_IDEX__5 /*!< Divide by 5 */ +#define TAIDEX__6 TIMER_A_EX0_IDEX__6 /*!< Divide by 6 */ +#define TAIDEX__7 TIMER_A_EX0_IDEX__7 /*!< Divide by 7 */ +#define TAIDEX__8 TIMER_A_EX0_IDEX__8 /*!< Divide by 8 */ + +/****************************************************************************** +* WDT_A Bits (legacy section) +******************************************************************************/ +/* WDTCTL[WDTIS] Bits */ +#define WDTIS_OFS WDT_A_CTL_IS_OFS /*!< WDTIS Offset */ +#define WDTIS_M WDT_A_CTL_IS_MASK /*!< Watchdog timer interval select */ +#define WDTIS0 WDT_A_CTL_IS0 /*!< WDTIS Bit 0 */ +#define WDTIS1 WDT_A_CTL_IS1 /*!< WDTIS Bit 1 */ +#define WDTIS2 WDT_A_CTL_IS2 /*!< WDTIS Bit 2 */ +#define WDTIS_0 WDT_A_CTL_IS_0 /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ +#define WDTIS_1 WDT_A_CTL_IS_1 /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ +#define WDTIS_2 WDT_A_CTL_IS_2 /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ +#define WDTIS_3 WDT_A_CTL_IS_3 /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ +#define WDTIS_4 WDT_A_CTL_IS_4 /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ +#define WDTIS_5 WDT_A_CTL_IS_5 /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ +#define WDTIS_6 WDT_A_CTL_IS_6 /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ +#define WDTIS_7 WDT_A_CTL_IS_7 /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ +/* WDTCTL[WDTCNTCL] Bits */ +#define WDTCNTCL_OFS WDT_A_CTL_CNTCL_OFS /*!< WDTCNTCL Offset */ +#define WDTCNTCL WDT_A_CTL_CNTCL /*!< Watchdog timer counter clear */ +/* WDTCTL[WDTTMSEL] Bits */ +#define WDTTMSEL_OFS WDT_A_CTL_TMSEL_OFS /*!< WDTTMSEL Offset */ +#define WDTTMSEL WDT_A_CTL_TMSEL /*!< Watchdog timer mode select */ +/* WDTCTL[WDTSSEL] Bits */ +#define WDTSSEL_OFS WDT_A_CTL_SSEL_OFS /*!< WDTSSEL Offset */ +#define WDTSSEL_M WDT_A_CTL_SSEL_MASK /*!< Watchdog timer clock source select */ +#define WDTSSEL0 WDT_A_CTL_SSEL0 /*!< WDTSSEL Bit 0 */ +#define WDTSSEL1 WDT_A_CTL_SSEL1 /*!< WDTSSEL Bit 1 */ +#define WDTSSEL_0 WDT_A_CTL_SSEL_0 /*!< SMCLK */ +#define WDTSSEL_1 WDT_A_CTL_SSEL_1 /*!< ACLK */ +#define WDTSSEL_2 WDT_A_CTL_SSEL_2 /*!< VLOCLK */ +#define WDTSSEL_3 WDT_A_CTL_SSEL_3 /*!< BCLK */ +#define WDTSSEL__SMCLK WDT_A_CTL_SSEL__SMCLK /*!< SMCLK */ +#define WDTSSEL__ACLK WDT_A_CTL_SSEL__ACLK /*!< ACLK */ +#define WDTSSEL__VLOCLK WDT_A_CTL_SSEL__VLOCLK /*!< VLOCLK */ +#define WDTSSEL__BCLK WDT_A_CTL_SSEL__BCLK /*!< BCLK */ +/* WDTCTL[WDTHOLD] Bits */ +#define WDTHOLD_OFS WDT_A_CTL_HOLD_OFS /*!< WDTHOLD Offset */ +#define WDTHOLD WDT_A_CTL_HOLD /*!< Watchdog timer hold */ +/* WDTCTL[WDTPW] Bits */ +#define WDTPW_OFS WDT_A_CTL_PW_OFS /*!< WDTPW Offset */ +#define WDTPW_M WDT_A_CTL_PW_MASK /*!< Watchdog timer password */ +/* Pre-defined bitfield values */ +#define WDTPW WDT_A_CTL_PW /*!< WDT Key Value for WDT write access */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MSP432P401R_CLASSIC_H__ */ diff --git a/inc/msp_compatibility.h b/inc/msp_compatibility.h new file mode 100644 index 0000000..02cc310 --- /dev/null +++ b/inc/msp_compatibility.h @@ -0,0 +1,326 @@ +//***************************************************************************** +// +// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// MSP430 intrinsic redefinitions for use with MSP432 Family Devices +// +//**************************************************************************** + +/****************************************************************************** +* Definitions for 8/16/32-bit wide memory access * +******************************************************************************/ +#define HWREG8(x) (*((volatile uint8_t *)(x))) +#define HWREG16(x) (*((volatile uint16_t *)(x))) +#define HWREG32(x) (*((volatile uint32_t *)(x))) +#define HWREG(x) (HWREG16(x)) +#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x))) +#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1))) +#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x))) +#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1))) + +/****************************************************************************** +* Definitions for 8/16/32-bit wide bit band access * +******************************************************************************/ +#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) +#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) +#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) + +// Intrinsics with ARM equivalents +#if defined ( __TI_ARM__ ) /* TI CGT Compiler */ + +#define __sleep() __wfi() +#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } +#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } +#define __get_SP_register() __get_MSP() +#define __set_SP_register(x) __set_MSP(x) +#define __get_interrupt_state() __get_PRIMASK() +#define __set_interrupt_state(x) __set_PRIMASK(x) +#define __enable_interrupt() _enable_IRQ() +#define __enable_interrupts() _enable_IRQ() +#define __disable_interrupt() _disable_IRQ() +#define __disable_interrupts() _disable_IRQ() +#define __no_operation() __asm(" nop") + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ + +#include + +#define __INLINE inline +#define __sleep() __WFI() +#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } +#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } +#define __get_SP_register() __get_MSP() +#define __set_SP_register() __set_MSP() +#define __enable_interrupts() __asm(" cpsie i") +#define __disable_interrupts() __asm(" cpsid i") + +#if (__VER__ < 8020002) + #define __get_interrupt_state() __get_PRIMASK() + #define __set_interrupt_state(x) __set_PRIMASK(x) + #define __enable_interrupt() __asm(" cpsie i") + #define __disable_interrupt() __asm(" cpsid i") + #define __no_operation() __asm(" nop") +#else + #include "intrinsics.h" +#endif + +// Intrinsics without ARM equivalents +#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } + +#elif defined ( __CC_ARM ) /* ARM Compiler */ + +#define __sleep() __wfi() +#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } +#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } +#define __get_SP_register() __get_MSP() +#define __set_SP_register(x) __set_MSP(x) +#define __get_interrupt_state() __get_PRIMASK() +#define __set_interrupt_state(x) __set_PRIMASK(x) +#define __enable_interrupt() __asm(" cpsie i") +#define __enable_interrupts() __asm(" cpsie i") +#define __disable_interrupt() __asm(" cpsid i") +#define __disable_interrupts() __asm(" cpsid i") +#define __no_operation() __asm(" nop") + +// Intrinsics without ARM equivalents +#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } + +#elif defined ( __GNUC__ ) /* GCC Compiler */ +#undef __wfi +#define __wfi() __asm(" wfi") +#define __sleep() __wfi() +#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } +#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } +#define __get_SP_register() __get_MSP() +#define __set_SP_register(x) __set_MSP(x) +#define __get_interrupt_state() __get_PRIMASK() +#define __set_interrupt_state(x) __set_PRIMASK(x) +#define __enable_interrupt() __asm(" cpsie i") +#define __enable_interrupts() __asm(" cpsie i") +#define __disable_interrupt() __asm(" cpsid i") +#define __disable_interrupts() __asm(" cpsid i") +#define __no_operation() __asm(" nop") + +// Intrinsics without ARM equivalents +#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } +#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } +#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } + +#endif + +// Intrinsics without ARM equivalents +#define __low_power_mode_0() { __sleep(); } +#define __low_power_mode_1() { __sleep(); } +#define __low_power_mode_2() { __sleep(); } +#define __low_power_mode_3() { __deep_sleep(); } +#define __low_power_mode_4() { __deep_sleep(); } +#define __data16_read_addr(x) (*((volatile uint32_t *)(x))) +#define __data20_read_char(x) (*((volatile uint8_t *)(x))) +#define __data20_read_short(x) (*((volatile uint16_t *)(x))) +#define __data20_read_long(x) (*((volatile uint32_t *)(x))) +#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) } +#define __get_SR_register() 0 +#define __get_SR_register_on_exit() 0 + +// the following defines are deprecated and will be removed in future releases +#define ATLBASE ALTBASE +#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /*!< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /*!< for furture use. Defaults to DCOCLK. Do not use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ +#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ + /* compatibilities. */ + /* CS_CTL2[LFXTAGCOFF] Bits */ +#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /*!< LFXTAGCOFF Bit Offset */ +#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /*!< Disables the automatic gain control of the LFXT crystal */ + +/* CS_CTL3[FCNTHF2] Bits */ +#define CS_CTL3_FCNTHF2_OFS ( 8) /*!< FCNTHF2 Bit Offset */ +#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /*!< FCNTHF2 Bit Mask */ +#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /*!< FCNTHF2 Bit 0 */ +#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /*!< FCNTHF2 Bit 1 */ +#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ +#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /*!< 4096 cycles */ +#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /*!< 8192 cycles */ +#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /*!< 16384 cycles */ +#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ +#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /*!< 4096 cycles */ +#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /*!< 8192 cycles */ +#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /*!< 16384 cycles */ +/* CS_CTL3[RFCNTHF2] Bits */ +#define CS_CTL3_RFCNTHF2_OFS (10) /*!< RFCNTHF2 Bit Offset */ +#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /*!< Reset start fault counter for HFXT2 */ +/* CS_CTL3[FCNTHF2_EN] Bits */ +#define CS_CTL3_FCNTHF2_EN_OFS (11) /*!< FCNTHF2_EN Bit Offset */ +#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /*!< Enable start fault counter for HFXT2 */ +/* CS_STAT[HFXT2_ON] Bits */ +#define CS_STAT_HFXT2_ON_OFS ( 3) /*!< HFXT2_ON Bit Offset */ +#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /*!< HFXT2 status */ +/* CS_IE[HFXT2IE] Bits */ +#define CS_IE_HFXT2IE_OFS ( 2) /*!< HFXT2IE Bit Offset */ +#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag interrupt enable */ +/* CS_IE[FCNTHF2IE] Bits */ +#define CS_IE_FCNTHF2IE_OFS (10) /*!< FCNTHF2IE Bit Offset */ +#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /*!< Start fault counter interrupt enable HFXT2 */ +/* CS_IE[PLLOOLIE] Bits */ +#define CS_IE_PLLOOLIE_OFS (12) /*!< PLLOOLIE Bit Offset */ +#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt enable */ +/* CS_IE[PLLLOSIE] Bits */ +#define CS_IE_PLLLOSIE_OFS (13) /*!< PLLLOSIE Bit Offset */ +#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt enable */ +/* CS_IE[PLLOORIE] Bits */ +#define CS_IE_PLLOORIE_OFS (14) /*!< PLLOORIE Bit Offset */ +#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt enable */ +/* CS_IE[CALIE] Bits */ +#define CS_IE_CALIE_OFS (15) /*!< CALIE Bit Offset */ +#define CS_IE_CALIE ((uint32_t)0x00008000) /*!< REFCNT period counter interrupt enable */ +/* CS_IFG[HFXT2IFG] Bits */ +#define CS_IFG_HFXT2IFG_OFS ( 2) /*!< HFXT2IFG Bit Offset */ +#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag */ +/* CS_IFG[FCNTHF2IFG] Bits */ +#define CS_IFG_FCNTHF2IFG_OFS (11) /*!< FCNTHF2IFG Bit Offset */ +#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /*!< Start fault counter interrupt flag HFXT2 */ +/* CS_IFG[PLLOOLIFG] Bits */ +#define CS_IFG_PLLOOLIFG_OFS (12) /*!< PLLOOLIFG Bit Offset */ +#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt flag */ +/* CS_IFG[PLLLOSIFG] Bits */ +#define CS_IFG_PLLLOSIFG_OFS (13) /*!< PLLLOSIFG Bit Offset */ +#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt flag */ +/* CS_IFG[PLLOORIFG] Bits */ +#define CS_IFG_PLLOORIFG_OFS (14) /*!< PLLOORIFG Bit Offset */ +#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt flag */ +/* CS_IFG[CALIFG] Bits */ +#define CS_IFG_CALIFG_OFS (15) /*!< CALIFG Bit Offset */ +#define CS_IFG_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter expired */ +/* CS_CLRIFG[CLR_HFXT2IFG] Bits */ +#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /*!< CLR_HFXT2IFG Bit Offset */ +#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /*!< Clear HFXT2 oscillator fault interrupt flag */ +/* CS_CLRIFG[CLR_CALIFG] Bits */ +#define CS_CLRIFG_CLR_CALIFG_OFS (15) /*!< CLR_CALIFG Bit Offset */ +#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter clear interrupt flag */ +/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */ +#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /*!< CLR_FCNTHF2IFG Bit Offset */ +#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter clear interrupt flag HFXT2 */ +/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */ +#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /*!< CLR_PLLOOLIFG Bit Offset */ +#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock clear interrupt flag */ +/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */ +#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /*!< CLR_PLLLOSIFG Bit Offset */ +#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal clear interrupt flag */ +/* CS_CLRIFG[CLR_PLLOORIFG] Bits */ +#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /*!< CLR_PLLOORIFG Bit Offset */ +#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range clear interrupt flag */ +/* CS_SETIFG[SET_HFXT2IFG] Bits */ +#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /*!< SET_HFXT2IFG Bit Offset */ +#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /*!< Set HFXT2 oscillator fault interrupt flag */ +/* CS_SETIFG[SET_CALIFG] Bits */ +#define CS_SETIFG_SET_CALIFG_OFS (15) /*!< SET_CALIFG Bit Offset */ +#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter set interrupt flag */ +/* CS_SETIFG[SET_FCNTHF2IFG] Bits */ +#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /*!< SET_FCNTHF2IFG Bit Offset */ +#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter set interrupt flag HFXT2 */ +/* CS_SETIFG[SET_PLLOOLIFG] Bits */ +#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /*!< SET_PLLOOLIFG Bit Offset */ +#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock set interrupt flag */ +/* CS_SETIFG[SET_PLLLOSIFG] Bits */ +#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /*!< SET_PLLLOSIFG Bit Offset */ +#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal set interrupt flag */ +/* CS_SETIFG[SET_PLLOORIFG] Bits */ +#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /*!< SET_PLLOORIFG Bit Offset */ +#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range set interrupt flag */ + +/* EUSCI_x_CTLW0[SSEL] Bits */ +#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ +#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ +#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ + +/* RSTCTL_PSSRESET_STAT[SVSL] Bits */ +#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /*!< SVSL Bit Offset */ +#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /*!< Indicates if POR was caused by an SVSL trip condition in the PSS */ + +/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */ +#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /*!< DBG_SEC_ACT Bit Offset */ +#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /*!< Debug Security active */ +/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */ +#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /*!< JTAG_SWD_LOCK_ACT Bit Offset */ +#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /*!< Indicates if JTAG and SWD Lock is active */ +/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */ +#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /*!< IP_PROT_ACT Bit Offset */ +#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /*!< Indicates if IP protection is active */ + diff --git a/inc/system_msp432p401r.h b/inc/system_msp432p401r.h new file mode 100644 index 0000000..7df3ea1 --- /dev/null +++ b/inc/system_msp432p401r.h @@ -0,0 +1,92 @@ +/**************************************************************************//** +* @file system_msp432p401r.h +* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for +* MSP432P401R +* @version 3.231 +* @date 01/26/18 +* +* @note View configuration instructions embedded in comments +* +******************************************************************************/ +//***************************************************************************** +// +// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef SYSTEM_MSP432P401R_H +#define SYSTEM_MSP432P401R_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * + * Performs the following initialization steps: + * 1. Enables the FPU + * 2. Halts the WDT + * 3. Enables all SRAM banks + * 4. Sets up power __REGULATOR and VCORE + * 5. Enable Flash wait states if needed + * 6. Change MCLK to desired frequency + * 7. Enable Flash read buffering + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_MSP432P401R_H */ + diff --git a/lab1/Makefile b/lab1/Makefile index e05f726..19e8a83 100644 --- a/lab1/Makefile +++ b/lab1/Makefile @@ -5,13 +5,13 @@ CC = arm-none-eabi-gcc # is installed. ARMGCC_ROOT := ${shell dirname ${shell readlink ${shell which ${CC}}}}/.. -ROOT ?= $(abspath ../..) +ROOT ?= $(abspath ..) OBJECTS = main.o system.o startup.o NAME = lab -CFLAGS = -I.. \ +CFLAGS = -I.. -I../inc \ -I$(ROOT)/source \ -I$(ROOT)/source/third_party/CMSIS/Include \ -D__MSP432P401R__ \ diff --git a/lab1/main.c b/lab1/main.c index 2be3cb9..3376c07 100644 --- a/lab1/main.c +++ b/lab1/main.c @@ -1,7 +1,7 @@ #include #include -#include "ti/devices/msp432p4xx/inc/msp432p401r.h" +#include "inc/msp432p401r.h" #define SW1 0x02 // on the left side of the LaunchPad board #define SW2 0x10 // on the right side of the LaunchPad board diff --git a/system.c b/system.c index f58d753..79929c0 100644 --- a/system.c +++ b/system.c @@ -43,7 +43,7 @@ //***************************************************************************** #include -#include "ti/devices/msp432p4xx/inc/msp432p401r.h" +#include "inc/msp432p401r.h" /*--------------------- Configuration Instructions ---------------------------- 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: