75 lines
4.1 KiB
C
75 lines
4.1 KiB
C
#include "clock.h"
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#include "inc/msp432p401r.h"
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// Configure the system clock to run at the fastest
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// and most accurate settings.
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uint32_t pre_wait = 0; // loops between BSP_Clock_InitFastest() called and PCM idle (expect 0)
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uint32_t cpm_wait = 0; // loops between Power Active Mode Request and Current Power Mode matching requested mode (expect small)
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uint32_t post_wait = 0; // loops between Current Power Mode matching requested mode and PCM module idle (expect about 0)
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uint32_t iflags = 0; // non-zero if transition is invalid
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uint32_t crystal_stable = 0; // loops before the crystal stabilizes (expect small)
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void ClockInit48MHz(void) {
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// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
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while (PCM->CTL1 & 0x00000100) {
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pre_wait++;
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if (pre_wait >= 100000) {
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return; // time out error
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}
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}
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// request power active mode LDO VCORE1 to support the 48 MHz frequency
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PCM->CTL0 = (PCM->CTL0 & ~0xFFFF000F) | // clear PCMKEY bit field and AMR bit field
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0x695A0000 | // write the proper PCM key to unlock write access
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0x00000001; // request power active mode LDO VCORE1
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// check if the transition is invalid (see Figure 7-3 on p344 of datasheet)
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if (PCM->IFG & 0x00000004) {
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iflags = PCM->IFG; // bit 2 set on active mode transition invalid; bits 1-0 are for LPM-related errors; bit 6 is for DC-DC-related error
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PCM->CLRIFG = 0x00000004; // clear the transition invalid flag
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// to do: look at CPM bit field in PCMCTL0, figure out what mode you're in, and step through the chart to transition to the mode you want
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// or be lazy and do nothing; this should work out of reset at least, but it WILL NOT work if Clock_Int32kHz() or Clock_InitLowPower() has been called
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return;
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}
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// wait for the CPM (Current Power Mode) bit field to reflect a change to active mode LDO VCORE1
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while ((PCM->CTL0 & 0x00003F00) != 0x00000100) {
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cpm_wait++;
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if (cpm_wait >= 500000) {
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return; // time out error
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}
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}
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// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
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while (PCM->CTL1 & 0x00000100) {
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post_wait++;
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if (post_wait >= 100000) {
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return; // time out error
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}
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}
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// initialize PJ.3 and PJ.2 and make them HFXT (PJ.3 built-in 48 MHz crystal out; PJ.2 built-in 48 MHz crystal in)
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PJ->SEL0 |= 0x0C;
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PJ->SEL1 &= ~0x0C; // configure built-in 48 MHz crystal for HFXT operation
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CS->KEY = 0x695A; // unlock CS module for register access
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CS->CTL2 = (CS->CTL2 & ~0x00700000) | // clear HFXTFREQ bit field
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0x00600000 | // configure for 48 MHz external crystal
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0x00010000 | // HFXT oscillator drive selection for crystals >4 MHz
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0x01000000; // enable HFXT
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CS->CTL2 &= ~0x02000000; // disable high-frequency crystal bypass
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// wait for the HFXT clock to stabilize
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while (CS->IFG & 0x00000002) {
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CS->CLRIFG = 0x00000002; // clear the HFXT oscillator interrupt flag
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crystal_stable++;
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if (crystal_stable > 100000) {
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return; // time out error
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}
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}
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// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 0
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FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~0x0000F000) | FLCTL_BANK0_RDCTL_WAIT_2;
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// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 1
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FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~0x0000F000) | FLCTL_BANK1_RDCTL_WAIT_2;
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CS->CTL1 = 0x20000000 | // configure for SMCLK divider /4
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0x00100000 | // configure for HSMCLK divider /2
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0x00000200 | // configure for ACLK sourced from REFOCLK
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0x00000050 | // configure for SMCLK and HSMCLK sourced from HFXTCLK
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0x00000005; // configure for MCLK sourced from HFXTCLK
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CS->KEY = 0; // lock CS module from unintended access
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}
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