327 lines
25 KiB
C
327 lines
25 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// MSP430 intrinsic redefinitions for use with MSP432 Family Devices
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//
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//****************************************************************************
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/******************************************************************************
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* Definitions for 8/16/32-bit wide memory access *
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******************************************************************************/
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#define HWREG8(x) (*((volatile uint8_t *)(x)))
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#define HWREG16(x) (*((volatile uint16_t *)(x)))
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#define HWREG32(x) (*((volatile uint32_t *)(x)))
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#define HWREG(x) (HWREG16(x))
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#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
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#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
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#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
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#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
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/******************************************************************************
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* Definitions for 8/16/32-bit wide bit band access *
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******************************************************************************/
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#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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// Intrinsics with ARM equivalents
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#if defined ( __TI_ARM__ ) /* TI CGT Compiler */
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#define __sleep() __wfi()
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#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
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#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
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#define __get_SP_register() __get_MSP()
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#define __set_SP_register(x) __set_MSP(x)
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#define __get_interrupt_state() __get_PRIMASK()
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#define __set_interrupt_state(x) __set_PRIMASK(x)
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#define __enable_interrupt() _enable_IRQ()
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#define __enable_interrupts() _enable_IRQ()
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#define __disable_interrupt() _disable_IRQ()
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#define __disable_interrupts() _disable_IRQ()
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#define __no_operation() __asm(" nop")
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#elif defined ( __ICCARM__ ) /* IAR Compiler */
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#include <stdint.h>
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#define __INLINE inline
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#define __sleep() __WFI()
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#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
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#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
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#define __get_SP_register() __get_MSP()
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#define __set_SP_register() __set_MSP()
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#define __enable_interrupts() __asm(" cpsie i")
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#define __disable_interrupts() __asm(" cpsid i")
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#if (__VER__ < 8020002)
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#define __get_interrupt_state() __get_PRIMASK()
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#define __set_interrupt_state(x) __set_PRIMASK(x)
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#define __enable_interrupt() __asm(" cpsie i")
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#define __disable_interrupt() __asm(" cpsid i")
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#define __no_operation() __asm(" nop")
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#else
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#include "intrinsics.h"
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#endif
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// Intrinsics without ARM equivalents
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#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
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#elif defined ( __CC_ARM ) /* ARM Compiler */
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#define __sleep() __wfi()
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#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
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#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
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#define __get_SP_register() __get_MSP()
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#define __set_SP_register(x) __set_MSP(x)
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#define __get_interrupt_state() __get_PRIMASK()
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#define __set_interrupt_state(x) __set_PRIMASK(x)
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#define __enable_interrupt() __asm(" cpsie i")
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#define __enable_interrupts() __asm(" cpsie i")
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#define __disable_interrupt() __asm(" cpsid i")
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#define __disable_interrupts() __asm(" cpsid i")
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#define __no_operation() __asm(" nop")
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// Intrinsics without ARM equivalents
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#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
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#elif defined ( __GNUC__ ) /* GCC Compiler */
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#undef __wfi
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#define __wfi() __asm(" wfi")
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#define __sleep() __wfi()
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#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
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#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
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#define __get_SP_register() __get_MSP()
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#define __set_SP_register(x) __set_MSP(x)
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#define __get_interrupt_state() __get_PRIMASK()
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#define __set_interrupt_state(x) __set_PRIMASK(x)
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#define __enable_interrupt() __asm(" cpsie i")
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#define __enable_interrupts() __asm(" cpsie i")
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#define __disable_interrupt() __asm(" cpsid i")
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#define __disable_interrupts() __asm(" cpsid i")
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#define __no_operation() __asm(" nop")
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// Intrinsics without ARM equivalents
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#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
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#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
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#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
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#endif
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// Intrinsics without ARM equivalents
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#define __low_power_mode_0() { __sleep(); }
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#define __low_power_mode_1() { __sleep(); }
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#define __low_power_mode_2() { __sleep(); }
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#define __low_power_mode_3() { __deep_sleep(); }
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#define __low_power_mode_4() { __deep_sleep(); }
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#define __data16_read_addr(x) (*((volatile uint32_t *)(x)))
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#define __data20_read_char(x) (*((volatile uint8_t *)(x)))
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#define __data20_read_short(x) (*((volatile uint16_t *)(x)))
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#define __data20_read_long(x) (*((volatile uint32_t *)(x)))
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#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) }
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#define __get_SR_register() 0
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#define __get_SR_register_on_exit() 0
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// the following defines are deprecated and will be removed in future releases
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#define ATLBASE ALTBASE
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#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /*!< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /*!< for furture use. Defaults to DCOCLK. Do not use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
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/* compatibilities. */
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/* CS_CTL2[LFXTAGCOFF] Bits */
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#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /*!< LFXTAGCOFF Bit Offset */
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#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /*!< Disables the automatic gain control of the LFXT crystal */
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/* CS_CTL3[FCNTHF2] Bits */
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#define CS_CTL3_FCNTHF2_OFS ( 8) /*!< FCNTHF2 Bit Offset */
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#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /*!< FCNTHF2 Bit Mask */
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#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /*!< FCNTHF2 Bit 0 */
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#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /*!< FCNTHF2 Bit 1 */
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#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /*!< 2048 cycles */
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#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /*!< 4096 cycles */
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#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /*!< 8192 cycles */
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#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /*!< 16384 cycles */
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#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */
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#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /*!< 4096 cycles */
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#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /*!< 8192 cycles */
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#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /*!< 16384 cycles */
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/* CS_CTL3[RFCNTHF2] Bits */
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#define CS_CTL3_RFCNTHF2_OFS (10) /*!< RFCNTHF2 Bit Offset */
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#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /*!< Reset start fault counter for HFXT2 */
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/* CS_CTL3[FCNTHF2_EN] Bits */
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#define CS_CTL3_FCNTHF2_EN_OFS (11) /*!< FCNTHF2_EN Bit Offset */
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#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /*!< Enable start fault counter for HFXT2 */
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/* CS_STAT[HFXT2_ON] Bits */
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#define CS_STAT_HFXT2_ON_OFS ( 3) /*!< HFXT2_ON Bit Offset */
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#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /*!< HFXT2 status */
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/* CS_IE[HFXT2IE] Bits */
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#define CS_IE_HFXT2IE_OFS ( 2) /*!< HFXT2IE Bit Offset */
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#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag interrupt enable */
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/* CS_IE[FCNTHF2IE] Bits */
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#define CS_IE_FCNTHF2IE_OFS (10) /*!< FCNTHF2IE Bit Offset */
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#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /*!< Start fault counter interrupt enable HFXT2 */
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/* CS_IE[PLLOOLIE] Bits */
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#define CS_IE_PLLOOLIE_OFS (12) /*!< PLLOOLIE Bit Offset */
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#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt enable */
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/* CS_IE[PLLLOSIE] Bits */
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#define CS_IE_PLLLOSIE_OFS (13) /*!< PLLLOSIE Bit Offset */
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#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt enable */
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/* CS_IE[PLLOORIE] Bits */
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#define CS_IE_PLLOORIE_OFS (14) /*!< PLLOORIE Bit Offset */
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#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt enable */
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/* CS_IE[CALIE] Bits */
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#define CS_IE_CALIE_OFS (15) /*!< CALIE Bit Offset */
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#define CS_IE_CALIE ((uint32_t)0x00008000) /*!< REFCNT period counter interrupt enable */
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/* CS_IFG[HFXT2IFG] Bits */
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#define CS_IFG_HFXT2IFG_OFS ( 2) /*!< HFXT2IFG Bit Offset */
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#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag */
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/* CS_IFG[FCNTHF2IFG] Bits */
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#define CS_IFG_FCNTHF2IFG_OFS (11) /*!< FCNTHF2IFG Bit Offset */
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#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /*!< Start fault counter interrupt flag HFXT2 */
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/* CS_IFG[PLLOOLIFG] Bits */
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#define CS_IFG_PLLOOLIFG_OFS (12) /*!< PLLOOLIFG Bit Offset */
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#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt flag */
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/* CS_IFG[PLLLOSIFG] Bits */
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#define CS_IFG_PLLLOSIFG_OFS (13) /*!< PLLLOSIFG Bit Offset */
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#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt flag */
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/* CS_IFG[PLLOORIFG] Bits */
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#define CS_IFG_PLLOORIFG_OFS (14) /*!< PLLOORIFG Bit Offset */
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#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt flag */
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/* CS_IFG[CALIFG] Bits */
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#define CS_IFG_CALIFG_OFS (15) /*!< CALIFG Bit Offset */
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#define CS_IFG_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter expired */
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/* CS_CLRIFG[CLR_HFXT2IFG] Bits */
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#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /*!< CLR_HFXT2IFG Bit Offset */
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#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /*!< Clear HFXT2 oscillator fault interrupt flag */
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/* CS_CLRIFG[CLR_CALIFG] Bits */
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#define CS_CLRIFG_CLR_CALIFG_OFS (15) /*!< CLR_CALIFG Bit Offset */
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#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter clear interrupt flag */
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/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */
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#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /*!< CLR_FCNTHF2IFG Bit Offset */
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#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter clear interrupt flag HFXT2 */
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/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */
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#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /*!< CLR_PLLOOLIFG Bit Offset */
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#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock clear interrupt flag */
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/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */
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#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /*!< CLR_PLLLOSIFG Bit Offset */
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#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal clear interrupt flag */
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/* CS_CLRIFG[CLR_PLLOORIFG] Bits */
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#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /*!< CLR_PLLOORIFG Bit Offset */
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#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range clear interrupt flag */
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/* CS_SETIFG[SET_HFXT2IFG] Bits */
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#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /*!< SET_HFXT2IFG Bit Offset */
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#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /*!< Set HFXT2 oscillator fault interrupt flag */
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/* CS_SETIFG[SET_CALIFG] Bits */
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#define CS_SETIFG_SET_CALIFG_OFS (15) /*!< SET_CALIFG Bit Offset */
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#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter set interrupt flag */
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/* CS_SETIFG[SET_FCNTHF2IFG] Bits */
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#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /*!< SET_FCNTHF2IFG Bit Offset */
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#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter set interrupt flag HFXT2 */
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/* CS_SETIFG[SET_PLLOOLIFG] Bits */
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#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /*!< SET_PLLOOLIFG Bit Offset */
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#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock set interrupt flag */
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/* CS_SETIFG[SET_PLLLOSIFG] Bits */
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#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /*!< SET_PLLLOSIFG Bit Offset */
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#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal set interrupt flag */
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/* CS_SETIFG[SET_PLLOORIFG] Bits */
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#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /*!< SET_PLLOORIFG Bit Offset */
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#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range set interrupt flag */
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/* EUSCI_x_CTLW0[SSEL] Bits */
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#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */
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#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */
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#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */
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/* RSTCTL_PSSRESET_STAT[SVSL] Bits */
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#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /*!< SVSL Bit Offset */
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#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /*!< Indicates if POR was caused by an SVSL trip condition in the PSS */
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/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */
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#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /*!< DBG_SEC_ACT Bit Offset */
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#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /*!< Debug Security active */
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/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */
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#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /*!< JTAG_SWD_LOCK_ACT Bit Offset */
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#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /*!< Indicates if JTAG and SWD Lock is active */
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/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */
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#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /*!< IP_PROT_ACT Bit Offset */
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#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /*!< Indicates if IP protection is active */
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