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RISC-V_cpu
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Single cycle RISC-V cpu designed for my computer architecture class
2 Commits 1 Branch 0 Tags 66 KiB
Verilog 96.4%
Assembly 3.6%
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README.md

Single cycle RISC-V cpu in verilog. Supported instructions are: add, addi, and, sub, slt, div, beq, blt, lw, sw, lui, jal, jalr, auipc, sll, srl, sra